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The article says that Apple isn't making full use of the 5nm process node, and blames lack of SRAM scaling for it (presumably due to the large amount of L3 cache). Is this a problem that all processors are about to hit, or is this going to be overcome once process engineers are more familiar with 5nm?
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It's a story from a site that focuses on fabrication technology and the semiconductor market place. The topic is device density. This is of interest, even if it doesn't interest you.
I appreciate that it's of interest to some people. So is the node figure you denigrated in your original post, though.
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Unless they specifically opt out, almost all iOS apps will be available on Apple Silicon macs at launch.
It will probably run, but I wonder if the UI will be usable on macOS?
As someone with an 8 year old MacBook Pro that isn’t all that much slower than my 2019 16”.... I am so glad Apple is still pushing the envelope. Back in the old days we used to get a doubling of performance every year or two. Then Intel got into trouble and has been producing the same chips for what 4-5 years? Essentially just minor changes. It’s not really Apple’s fault that the rest of the industry is lagging so ba…
My 2013 high end 15" MBP gets pretty hot when I'm watching 1080p or higher videos. Chrome+YouTube is even worse, it even drops frames. Compiling Swift is even worse than that. I have a work-provided 16" MBP that does all these things effortlessly.
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My 2013 high end 15" MBP gets pretty hot when I'm watching 1080p or higher videos. Chrome+YouTube is even worse, it even drops frames. Compiling Swift is even worse than that. I have a work-provided 16" MBP that does all these things effortlessly.
Are they using the same amount of hardware acceleration? If one has support for VP9 and one doesn't, then most of that is not because the cores changed in performance, it's because the video decoder got rearranged.
As someone with an 8 year old MacBook Pro that isn’t all that much slower than my 2019 16”.... I am so glad Apple is still pushing the envelope. Back in the old days we used to get a doubling of performance every year or two. Then Intel got into trouble and has been producing the same chips for what 4-5 years? Essentially just minor changes. It’s not really Apple’s fault that the rest of the industry is lagging so ba…
My 2013 high end 15" MBP gets pretty hot when I'm watching 1080p or higher videos. Chrome+YouTube is even worse, it even drops frames. Compiling Swift is even worse than that. I have a work-provided 16" MBP that does all these things effortlessly.
As someone with an 8 year old MacBook Pro that isn’t all that much slower than my 2019 16”.... I am so glad Apple is still pushing the envelope. Back in the old days we used to get a doubling of performance every year or two. Then Intel got into trouble and has been producing the same chips for what 4-5 years? Essentially just minor changes. It’s not really Apple’s fault that the rest of the industry is lagging so ba…
Blaming Intel for the end to frequency scaling is overblown. The reality is that the entire field started to hit limitations imposed by physics on the current silicon trajectory. While transistors kept (and keep) getting smaller, it's diminishing returns squeezing clockspeed and single-core performance out of it. Instead, everything has been going into scaling horizontally with more cores and more cache.
Also the current gen high end laptop CPUs from Intel are still 14nm. Which they introduced in 2015 with broadwell [1]. Others have shown that’s it’s very possible to scale beyond 14nm, so there is good reason to blame Intel here!
1. https://ark.intel.com/content/www/us/en/ark/products/87719/i...
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Apple doesn't have an exclusive on 5 nm; it's also being used by Kirin 9000, Snapdragon 875, some Exynos, and a future Dimensity SoC.
I'm not sure how to square that claim with this sort of article: https://www.extremetech.com/computing/315186-apple-books-tsm...
Isn't this mostly TSMC's achievement? Can't their other clients reach the same density?
One consideration is that while we think of each transistor as individual and isolated, in reality they are simply wells of n and p type silicon with some oxides and metal thrown in. Because of this we can get unwanted parasitic components and latches. A BJT transistor for example is just a pattern of three silicon types, so it is somewhat inevitable that these will occur, whether they cause issues, and to what extent depends on the design.
Packing everything as tight as possible gives noise concerns, thermal concerns, signal integrity issues ect.
This is not to devalue the achievement of TSMC, but to state that design work is still a work as well.
I found this to be a pretty confusing article. I get that they are analyzing the new node, which is great, but the editorializing seems a bit premature to me. I also don't think the author understood the TMSC presentation. TMSC clearly said that is used a "model" of a typical SOC of 60% logic, 30% SRAM, and 10% analog. Then they said that for each category of thing, you could expect 1.8x, 1.35x, and 1.2x of shrink. I…