If you wanted to do something with a hardware root-of-trust, would the GDSII leak needed secrets (i.e. any private keys could be extracted by looking at what you're required to open up), or is that done in some special post-fab way?
Google offers free fabbing for 130nm open-source chips
181–190 of 404 posts
Re: Google offers free fabbing for 130nm open-source chips
#182Earlier quoted context omitted.
This isn't true. Writing open source software is more profitable: it's cheaper (because everyone works on it) and works better (because everyone works on it).
Do you have data to back this up? Because all accounts I've heard say that it's incredibly difficult to make money in open source.
Re: Google offers free fabbing for 130nm open-source chips
#183TFA doesn't really summarize what's available very well, so let me take a shot from a technical perspective: - 130 nm process built with Skywater foundry - Skywater Platform Development Kit (PDK) is currently digital-only - 40 projects will be selected for fabrication - 10 mm^2 area available per-project - Will use a standard harness with a RISC-V core and RAM - Each project will get back ~100 ICs - All projects must…
(Remember 130nm gave us the late models Pentium 3s, the second model P4s and some Athlons, though all of these had a bigger die size)
I'm thinking you could have some low power or very specific ICs, where these would shine as opposed to a generic FPGA solution
Re: Google offers free fabbing for 130nm open-source chips
#184Earlier quoted context omitted.
yes, but it depends on the program, that's what the whole ASIC industry for bitcoin mining is.
I was thinking about AutoDock Vina ( Molecular Docking Software ), I have literally 0 knowledege about hardware :( Then again, this is going to be a really fun experience
- Reimplement the whole thing, in your choice of language, strictly without consideration of performance, to concretely grasp the implementation.
- Rewrite your reimplementation efficiently, using profiling etc, and using SSE/AVX or related techniques if/as possible. (I noticed references to Monte Carlo simulation in the code, and found some noise online that suggests this is vectorizable. I don't understand how MC is being used in the code though.) FWIW assembly language is likely 95-99% not worth chasing instead of Rust or C; one of the few real-world scenarios that call for asm is software video decode/encode, which boils down to patterns of hardcore number crunching that compilers are regarded to optimize poorly. I do not know whether this program is slow because it is poorly optimized or slow because it is simply computationally expensive.
- Rewrite your implementation to run on a GPU, if possible, using OpenMP or CUDA. (This may require implementing your own engine that achieves the same goals as the existing engine, after you achieve a high-level understanding of why the engine works the way it does, because you may need to rearchitect the way the program works in order to cram it into a GPU.)
- Reimplement your implementation in VHDL so it will run on an FPGA.
- Retarget your VHDL so it can be fabbed on a fixed-function ASIC.
This would be my high-level Handwavy Armchair Guide to achieving what you want :)
It's possible that the GPGPU or FPGA milestones will give you a significantly appreciable many-x performance boost. That may be 2x or 10x or 100x; you will be able to find out what is possible almost immediately, as you build your brain-dead implementation and go down little research/analysis paths figuring out how everything works.
It's also possible that the current implementation is poorly designed, and that sticking a profiler on it may find low hanging fruit. Likewise, it's equally possible the current implementation is well-tuned above average (despite being written in C++).
Oh, I found this random link that may be uninteresting or useful: https://news.ycombinator.com/item?id=18628326
Re: Google offers free fabbing for 130nm open-source chips
#185Earlier quoted context omitted.
> Want a linter for your project? That's going to be $50k. the thing is that i think the open source software is a miracle that it even exists, and i don't find it strange that nowhere else has replicated the success. Because open source, at heart, is quite altruistic.
This isn't true. Writing open source software is more profitable: it's cheaper (because everyone works on it) and works better (because everyone works on it).
Re: Google offers free fabbing for 130nm open-source chips
#186Earlier quoted context omitted.
Not only is the software expensive it's often crap. By which I don't mean, oh no it doesn't look nice - crap as in productivity-harming. For example, Altium Designer is probably the most modern (not most powerful although close) PCB suite and yet despite costing thousands a seat it is a slow, clunky, single-threaded (in 2020) program (somehow uses 20% of a 7700k at 4.6GHz with an empty design). Discord also thinks th…
From what I can tell a lot of parametric design software is also single threaded. I felt like this is was an opportunity where usage of multiple cores could make Freecad stand out a little bit. Except Freecad uses opencascade as their kernel and they require you to sign a CLA just to download the git repository. Considering that barrier to just cloning the code I just decided to not contribute anything. They do offer…
git clone https://git.dev.opencascade.org/repos/occt.git
It's not well-advertised, but they do offer public read-only HTTP access to the git repository.[1] This URL really should be listed on the Resources page as well as the project summary in GitWeb.[1] https://dev.opencascade.org/index.php?q=node/1212#comment-86...
Re: Google offers free fabbing for 130nm open-source chips
#187I've spent some time in the chip industry. It is awful, backwards, and super far behind. I didn't appreciate the full power of open source until I saw an industry that operates without it. Want a linter for your project? That's going to be $50k. Also, it's an absolutely terrible linter by software standards. In software, linters combine the best ideas from thousands of engineers across dozens of companies building on…
I've been thinking about this a lot lately. In economics, the value of competition is well understood and widely lauded, but the power of cooperation seems to be valued much less - cooperation simply doesn't seem as fashionable. But the FOSS world gives me hope - it shows me a world where cooperation is encouraged, and works really, really well. Where the best available solution isn't just the one that was made by a…
however the line does blur when talking about blueprints and designs.
in any case, I think that free software movements are a sociological anomaly, I wonder if there is any academic research into this from an antropological or an historical economics viewpoint.
also, it seems to me that in some sense the entire market works in cooperation, just not very efficiently (it optimizes for other things than efficiency and is heavily distorted by subsidies and tariffs)
Re: Google offers free fabbing for 130nm open-source chips
#188Earlier quoted context omitted.
Sounds like there should be open source software for such a thing? I bet the software for laying out transistors and so on will suddenly become viable with something like this, good idea Google!
There is open source software, a good overview is on http://opencircuitdesign.com/qflow/index.html .
Re: Google offers free fabbing for 130nm open-source chips
#189Re: Google offers free fabbing for 130nm open-source chips
#190Earlier quoted context omitted.
I wouldn't count on it: I don't think Cadence internals have changed much since then. And if they were to, I'd say that Cadence itself isn't especially easy to use, nor complicated to replicate. It would feel more like a lock-in attempt. The gEDA project would be a good place to start a new layout-level EDA. It has the necessary tools for simulation, already. Synthesis and place-and-route tools exist, but there are m…
> The more complex part would be to integrate it with DRC (design rule check) If you have open-source design tool (including schematic simulation and verification), I think you will have open-source tool for physical verification. Assume that we still use rule check standard from Mentor Calibre, Assura. > Thinking about it, it's a good thing that node isn't too advanced. It reduces the design rules complexity by a fe…
Right, though the manufacturer will usually automatically run design rules checks on the submitted designs (they don't want you to endanger other people's components due to density or antenna rules). But I was mostly thinking of it being integrated with a manual layout drawing tool: that's a nice-to-have, but not necessary, and more complex for a drawing tool. If you leave that out, creating a drawing tool should be pretty straightforward.
> The smaller process, the more complex.
Hence my point: it's easier to start with a less-complex process.