Hacker News Board Hacker News, browsed like a classic message board
Live data from Hacker News

Google offers free fabbing for 130nm open-source chips

fossi-foundation.org

Post reply on HN
Print view View original

151–160 of 404 posts

Re: Google offers free fabbing for 130nm open-source chips

#151

Post by Taek »

I've spent some time in the chip industry. It is awful, backwards, and super far behind. I didn't appreciate the full power of open source until I saw an industry that operates without it.

Want a linter for your project? That's going to be $50k. Also, it's an absolutely terrible linter by software standards. In software, linters combine the best ideas from thousands of engineers across dozens of companies building on each other's ideas over multiple decades. In hardware, linters combine the best ideas of a single team, because everything is closed and proprietary and your own special 'secret sauce'.

In software, I can import things for free like nginx and mysql and we have insanely complex compilers like llvm that are completely free. In hardware, the equivalent libraries are both 1-2 orders of magnitude less sophisticated (a disadvantage of everyone absolutely refusing to share knowledge with each other and let other people build on your own ideas for free), and also are going to cost you 6+ figures for anything remotely involved.

Hardware is in the stone age of sophistication, and it entirely boils down to the fact that people don't work together to make bigger, more sophisticated projects. Genuinely would not surprise me if a strong open source community could push the capabilities of a 130nm stack beyond what many 7nm projects are capable of, simply because of the knowledge gap that would start to develop between the open and closed world.

Re: Google offers free fabbing for 130nm open-source chips

#152

Post by Taek »

why_only_15 wrote: post #8

How much has the power efficiency improved between 130nm and 7nm? Is it plausible to get better performance/watt for a custom chip on 130nm vs a software application running on a 7m chip? I get that hardware has other benefits but just wondering for accelerators where the cost/benefit starts to make sense.

I wasn't able to find great specifications for the 130nm process, but it looks like the difference in transistor size and efficiency is somewhere around 100x. For specialized applications, going from a CPU to an ASIC is usually around a 1000x performance gain.

So yes, for specific tasks like crypto operations or custom networking, you should be able to make a 130nm ASIC that is going to outperform a 7nm Ryzen. You are not going to be able to make a CPU core that's going to outperform a Ryzen however.

Re: Google offers free fabbing for 130nm open-source chips

#153

Post by Taek »

pjc50 wrote: post #83
awelkie wrote: post #67

Earlier quoted context omitted.

An open source WiFi chip would be super cool. I wonder how easy it would be to take the FPGA code from openwifi[0] and combine it with a radio on the same chip? [0] https://github.com/open-sdr/openwifi

The problem is that analogue IC design is a field that even digital IC design people regard as black magic. It's clearly possible for that to happen but the set of people who have the skills to do it is very narrow and most of them are probably prevented from doing it in their spare time by their employment agreements. I wonder how many "test chips" Google will let a non-expert team do to get it right? And whether th…

A big part of the "black magic" really comes down to insufficient tooling. And at least in hardware, insufficient tooling comes down to the fact that everything is open source and trade secret, and teams pretty much refuse to share knowledge with each other.

An open source community would go a long way to fixing an issue like this, and these "black magic" projects are actually a fantastic place for the open source world to get started, because it's an area where there's a ton of room for improvement over the status quo.

Re: Google offers free fabbing for 130nm open-source chips

#154

Post by ajb »

So, this doesn't appear to have been announced by google. It does seem to be real but the OP may be jumping the gun a bit.

The authoritative source seems to be the slides of this guy at google: https://docs.google.com/presentation/d/e/2PACX-1vRtwZPc8ykkk...

From the slides this is "current plans, subject to change". This is an 'open source shuttle process'. Shuttle processes are a relatively cheap way of making small numbers of chips (it is actually more costly per chip, but the fixed cost is smaller). There will be some kind of approval process, and I would imagine that there is a capacity limit for both the number of chips and number of projects.

(I didn't have time to watch the talk, so the above is just from the slides)

Re: Google offers free fabbing for 130nm open-source chips

#155

Post by exikyut »

MayeulC wrote: post #68
PopeDotNinja wrote: post #50

Earlier quoted context omitted.

Maybe we could get Cadence to open source 20 year old software for the 20 year old 130nm chips!

I wouldn't count on it: I don't think Cadence internals have changed much since then. And if they were to, I'd say that Cadence itself isn't especially easy to use, nor complicated to replicate. It would feel more like a lock-in attempt. The gEDA project would be a good place to start a new layout-level EDA. It has the necessary tools for simulation, already. Synthesis and place-and-route tools exist, but there are m…

>> Maybe we could get Cadence to open source 20 year old software for the 20 year old 130nm chips!

"Haha, funny!"

> I wouldn't count on it: I don't think Cadence internals have changed much since then.

(Sigh)

Re: Google offers free fabbing for 130nm open-source chips

#156

Post by phkahler »

imtringued wrote: post #115
mhh__ wrote: post #41

Earlier quoted context omitted.

Not only is the software expensive it's often crap. By which I don't mean, oh no it doesn't look nice - crap as in productivity-harming. For example, Altium Designer is probably the most modern (not most powerful although close) PCB suite and yet despite costing thousands a seat it is a slow, clunky, single-threaded (in 2020) program (somehow uses 20% of a 7700k at 4.6GHz with an empty design). Discord also thinks th…

From what I can tell a lot of parametric design software is also single threaded. I felt like this is was an opportunity where usage of multiple cores could make Freecad stand out a little bit. Except Freecad uses opencascade as their kernel and they require you to sign a CLA just to download the git repository. Considering that barrier to just cloning the code I just decided to not contribute anything. They do offer…

SolveSpace now has some code paths multithreaded. It's not clear if this will make the next release but you can build from source with -fopenmp.

Like you say, it's kind of shocking to see one core running at 100 percent while the rest do nothing and the app is sluggish in 2020.

Re: Google offers free fabbing for 130nm open-source chips

#157

Post by BurnGpuBurn »

cottonseed wrote: post #133
BurnGpuBurn wrote: post #129

Are there any Risc-V designs that would plug in to this?

Yes, there are lots of open-source RISC-V cores. Tim Edwards of efabless has another talk about creating a RISC-V based ASIC SOC: https://www.youtube.com/watch?v=EsEcLZc0RO8 based on PicoRV: https://github.com/cliffordwolf/picorv32 . PicoRV is part of the efabless IP offerings. The chips will have a PicoRV harness on them.

Thanks!

Re: Google offers free fabbing for 130nm open-source chips

#158

Post by TedDoesntTalk »

baybal2 wrote: post #123
madengr wrote: post #103

Earlier quoted context omitted.

I thought most EDA companies put a stop to that with geographic licensing restrictions.

And this is the reason some companies have shift work... But that all means nothing for companies who buy Virtuoso copies from from guys trading WaReZ in pedestrian underpasses in BJ. A number of quite reputable SoC brands here in the PRD are known to be based on 100% pirated EDAs. This is not a critique, but a call to think about that a bit. In China, you can spin-up a microelectronics startup in under $1m, in USA,…

What is PRD? I’m guessing a country acronym?

Re: Google offers free fabbing for 130nm open-source chips

#159

Post by rwmj »

DCKing wrote: post #96
rwmj wrote: post #61

Earlier quoted context omitted.

How fast can those FPGAs be clocked? Is it better to have a free but small run of 68k ASICs which might have similar performance, or the potential to run a soft core on off-the-shelf FPGAs, at much higher cost per unit, but with the ability to rapidly iterate on the design?

The Apollo project here would be particularly suitable as they have already iterated on the design using FPGAs. The chip is already working as an FPGA and bringing tangible improvements: I'm assuming a 130nm ASIC version would be even better.

I'm not sure that assumption is necessarily right. As a general guide, on a cheap (sub $200) modern FPGA I can clock an RV64 core at 50-100 MHz. As you spend more on the FPGA, you can get higher clock rates and/or more cores. Also it should be possible to clock 32 bit cores higher (perhaps much higher) because there will be fewer data paths for internal routing to skew. On the other hand, modern RISC architectures are designed for this, whereas old 68k architectures may not be.
Post reply on HN