121–130 of 404 posts
This is fantastic, for many reasons, but the two that come immediately to mind are: - amazingly good for security. - finally the public at large will get to understand *in details* how an ASIC is designed.
Meta: please don’t use preformatted text for lists. It makes reading much harder, especially on narrower displays. Just put a blank line between each item, treat each as a paragraph.
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> Another exception might be low leakage construction, because that gets worse as the process gets smaller. This is only valuable if your chip is off almost all of the time and you want to squeeze down exactly how many nanoamps "off" actually consumes. No, you actually have more leakage at older nodes, what changes is the ratio of current spent on leakage vs. current spent doing something useful.
Doesn't leakage increase again below 22nm because of tunneling losses, though? Of course, the lower gate capacitance allows for lower switching losses. But adiabatic computing could theoretically recover switching losses, allowing for higher efficiency at older nodes. That can be approached by using an oscillating power supply for instance, to recover charges. If someone was to design something like this for this run…
You have tunnelling losses on bigger nodes as well, they are just not that dominant. Dielectrics got better as nodes shrank, and this is the reason FinFETs became practical (which switch faster, and more reliably on smaller nodes, but leak worse.)
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More like 6 figures per seat... It's actually a big part of why some silicon companies distribute themselves around timezones - so someone in Texas can fire up the software immediately when someone in the UK finishes work. It's not unusual to see an 'all engineering' email reminding to you close rather than minimize the software when you go to meetings.
I thought most EDA companies put a stop to that with geographic licensing restrictions.
But that all means nothing for companies who buy Virtuoso copies from from guys trading WaReZ in pedestrian underpasses in BJ.
A number of quite reputable SoC brands here in the PRD are known to be based on 100% pirated EDAs.
This is not a critique, but a call to think about that a bit.
In China, you can spin-up a microelectronics startup in under $1m, in USA, you will spend $1m to just buy a minimal EDA toolchain for the business.
Allwinner famously started with just $1m in capital, when disgruntled engineers from Actions decided to start their own business.
Strategically, could this be part of a response to Apple silicon? Or put another way, Apple and Google are both responding to Intel/the market’s failure to innovate enough in idiosyncratic manner: - Apple treats lower layers as core, and brings everything in-house; - Google treats lower layers as a threat and tries to open-source and commodify them to undermine competitors. I don’t mean this free fabbing can compete…
My first reaction was that it could be a recruitment drive of sorts to help build up their hardware team. Apple have been really smart in the last decade in buying up really good chip development teams and that is experience that is really hard to find.
They can outsource silicon development. Should not be a problem with their money.
In comparison to dotcom development teams, semi engineering teams are super cheap. In Taiwan, a good microelectronics PhD starting salary is USD $50k-60k...
Could someone explain, is there any advantage of producing a 130nm custom SoC compared to using a lower node FPGA for the same design?
Also for analog stuff you can't use FPGAs. And if you need an ASIC anyways for that why not include the digital part as well?
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You don't need your own mask; you can share with other customers. https://en.wikipedia.org/wiki/Multi-project_wafer_service https://www.tekmos.com/products/asics/reducing-the-asic-nre
Yes, this is what Google is doing with this project.
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Not only is the software expensive it's often crap. By which I don't mean, oh no it doesn't look nice - crap as in productivity-harming. For example, Altium Designer is probably the most modern (not most powerful although close) PCB suite and yet despite costing thousands a seat it is a slow, clunky, single-threaded (in 2020) program (somehow uses 20% of a 7700k at 4.6GHz with an empty design). Discord also thinks th…
From what I can tell a lot of parametric design software is also single threaded. I felt like this is was an opportunity where usage of multiple cores could make Freecad stand out a little bit. Except Freecad uses opencascade as their kernel and they require you to sign a CLA just to download the git repository. Considering that barrier to just cloning the code I just decided to not contribute anything. They do offer…
In the same vein something like ECAD tools don't use GPU-accelerated 2D rendering but instead use GDI and friends (which used to be HW-accelerated, but isn't since WDDM/Vista).
A lot of "easy" opportunities to improve UX and productivity.
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Lenses are used so the feature size on the mask is larger than the feature size on the wafer. https://www.nikon.com/about/technology/product/semiconductor...
Yes, but only few times. Still not clear how an initial mask has been produced? From file to mask - a kind of printer or a laser?
That sounds pretty huge. I've never seen on Hackaday or similar people getting small runs of chip fabbed. What are the broader implications of this? Will other fabs start to lower the barrier to production as well?
You generally don't do small runs of chips, unless cost is no object. The NRE costs of getting the masks made, even on older processes like these are still comfortably in the $X00,000 range, blowing past $1 million pretty quickly if you need a process that isn't ancient. That's without design software licenses, which can be hundreds of thousands more. So the minimum order quantity usually needs to be at least in the…
> $70K, 20 WEEKS, 100 SAMPLES
Note quite $50K, but close.