Hacker News Board Hacker News, browsed like a classic message board
Live data from Hacker News

Google offers free fabbing for 130nm open-source chips

fossi-foundation.org

Post reply on HN
Print view View original

91–100 of 404 posts

Re: Google offers free fabbing for 130nm open-source chips

#91

Post by quyleanh »

MayeulC wrote: post #68
PopeDotNinja wrote: post #50

Earlier quoted context omitted.

Maybe we could get Cadence to open source 20 year old software for the 20 year old 130nm chips!

I wouldn't count on it: I don't think Cadence internals have changed much since then. And if they were to, I'd say that Cadence itself isn't especially easy to use, nor complicated to replicate. It would feel more like a lock-in attempt. The gEDA project would be a good place to start a new layout-level EDA. It has the necessary tools for simulation, already. Synthesis and place-and-route tools exist, but there are m…

> The more complex part would be to integrate it with DRC (design rule check)

If you have open-source design tool (including schematic simulation and verification), I think you will have open-source tool for physical verification. Assume that we still use rule check standard from Mentor Calibre, Assura.

> Thinking about it, it's a good thing that node isn't too advanced. It reduces the design rules complexity by a few orders of magnitude.

The complexity depends on process. The smaller process, the more complex. There is thousands of rule check even on the old process (180nm, 130nm...).

Re: Google offers free fabbing for 130nm open-source chips

#92

Post by orbifold »

pjc50 wrote: post #81
janekm wrote: post #58

Earlier quoted context omitted.

My first reaction was that it could be a recruitment drive of sorts to help build up their hardware team. Apple have been really smart in the last decade in buying up really good chip development teams and that is experience that is really hard to find.

Does Google have a silicon team?

They have Norman Jouppi, he apparently was involved in the TPU design.

Re: Google offers free fabbing for 130nm open-source chips

#93

Post by asgeir »

ric2b wrote: post #78
novaRom wrote: post #57

Can someone please tell me how photo-masks are produced? I don't understand how can tiny features be printed at almost the same scale as a final structure? With a laser beam? Say, as an input you have a layer description (schematics) - how can you transfer it to a tiny scale so precisely to produce a mask?

They aren't built at the same scale, they're much larger than the final structure and lenses are used to scale the image down to the desired size. Here's a video form Intel on how they are made: https://youtu.be/u3ws0UebnSE Apparently they use "electron beams", not sure what those are, they sound similar to lasers but with electrons, from this video: https://youtu.be/PWV9pvdRBNY

Wouldn't that just be something like CRT? https://en.wikipedia.org/wiki/Cathode-ray_tube

Re: Google offers free fabbing for 130nm open-source chips

#94

Post by qaute »

blackrock wrote: post #10

I wonder if you can make micro machines at this level? The MEMS thing. I always wondered why you needed gearing mechanisms in a micro machine. Has there ever been a practical application for gears in MEMS?

> I always wondered why you needed gearing mechanisms in a micro machine. Has there ever been a practical application for gears in MEMS?

IIRC, Sandia Lab's SUMMiT V process (the source of videos like [1]) was funded in part to make mechanical latches and fail-safes for nuclear weapons, but I'm not sure what's currently in use for obvious reasons. I don't think they found many other practical applications, though experimentation led to TI's DMD chips, among other things.

Occasionally, MEMS techniques are used to make (relatively large) gears for watches.

I've also seen people try to use gears for microfluidic pumps, but I don't think any are much better than current simpler solid-state approaches.

[1] https://www.youtube.com/watch?v=GiG5czNvV4A

Re: Google offers free fabbing for 130nm open-source chips

#95

Post by xvilka »

I should note there's open source ASIC toolchain - OpenROAD[1][2]. I wonder if these can be integrated. You also can use SymbiFlow to run your prototype in FPGA[3][4].

[1] https://theopenroadproject.org/

[2] https://github.com/The-OpenROAD-Project/OpenROAD

[3] https://symbiflow.github.io/

[4] https://github.com/SymbiFlow

Re: Google offers free fabbing for 130nm open-source chips

#96

Post by DCKing »

rwmj wrote: post #61
DCKing wrote: post #31

From a hobbyist and preservation perspective, it would be cool if this could be used to produce some form of the Apollo 68080 core to revive the 68k architecture a little bit, and build out the Debian m68k port [0][1]. The last "big" 68k chips were produced in 1995 (that would be a 350nm process?) so this could be hugely improved on 130nm. The 68080 core is currently implemented in FPGAs only and is already the faste…

How fast can those FPGAs be clocked? Is it better to have a free but small run of 68k ASICs which might have similar performance, or the potential to run a soft core on off-the-shelf FPGAs, at much higher cost per unit, but with the ability to rapidly iterate on the design?

The Apollo project here would be particularly suitable as they have already iterated on the design using FPGAs. The chip is already working as an FPGA and bringing tangible improvements: I'm assuming a 130nm ASIC version would be even better.

Re: Google offers free fabbing for 130nm open-source chips

#97

Post by herio »

pjc50 wrote: post #77
DCKing wrote: post #31

From a hobbyist and preservation perspective, it would be cool if this could be used to produce some form of the Apollo 68080 core to revive the 68k architecture a little bit, and build out the Debian m68k port [0][1]. The last "big" 68k chips were produced in 1995 (that would be a 350nm process?) so this could be hugely improved on 130nm. The 68080 core is currently implemented in FPGAs only and is already the faste…

What happened to freescale/NXP "Coldfire"?

ColdFire is still around but is also not fully binary compatible with 68k. There have been attempts at making Amiga accelerator cards using Coldfires, but I don't think I've ever seen one that was fully finished.

Re: Google offers free fabbing for 130nm open-source chips

#98

Post by harpratap »

pjc50 wrote: post #81
janekm wrote: post #58

Earlier quoted context omitted.

My first reaction was that it could be a recruitment drive of sorts to help build up their hardware team. Apple have been really smart in the last decade in buying up really good chip development teams and that is experience that is really hard to find.

Does Google have a silicon team?

Manu Gulati - a very popular Silicon Engineer who worked at Apple left for Google. (He now works at Nuvia with other ex-Apple stalwarts)

Re: Google offers free fabbing for 130nm open-source chips

#99

Post by orbifold »

andy_ppp wrote: post #28
est31 wrote: post #6

This is amazing. I think the main reason why open source has taken off is because access to a computer is available to many people, and as cost is negligible, it only required free time and enough dedication + skill to be successful. For hardware though, each compile/edit/run cycle costs money, software often has 5-digit per seat licenses, and thus the number of people with enough resources to pursue this as a hobby…

Sounds like there should be open source software for such a thing? I bet the software for laying out transistors and so on will suddenly become viable with something like this, good idea Google!

There is open source software, a good overview is on http://opencircuitdesign.com/qflow/index.html.

Re: Google offers free fabbing for 130nm open-source chips

#100

Post by londons_explore »

andy_ppp wrote: post #84
leojfc wrote: post #53

Strategically, could this be part of a response to Apple silicon? Or put another way, Apple and Google are both responding to Intel/the market’s failure to innovate enough in idiosyncratic manner: - Apple treats lower layers as core, and brings everything in-house; - Google treats lower layers as a threat and tries to open-source and commodify them to undermine competitors. I don’t mean this free fabbing can compete…

I mean someone else said the software to design chips is 5 figures per seat so probably a multi billion dollar industry. My guess would be a cloud based chip design software is in the works. This would accelerate AI quite a bit I should think?

More like 6 figures per seat...

It's actually a big part of why some silicon companies distribute themselves around timezones - so someone in Texas can fire up the software immediately when someone in the UK finishes work.

It's not unusual to see an 'all engineering' email reminding to you close rather than minimize the software when you go to meetings.

Post reply on HN