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TSMC unveils 1.6nm process technology with backside power delivery

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Re: TSMC unveils 1.6nm process technology with backside power delivery

#81

Post by hackernudes »

Workaccount2 wrote: post #63
futureshock wrote: post #59

Comments about the marketing driven nm measurements aside, this still looks like another solid advance for TSMC. They are already significantly ahead of Samsung and Intel on transistor density. TSMC is at 197 MTr/mm2 wile Samsung is at 150 MTr/mm2 and Intel is at 123 MTr/mm2. This 1.6nm process will put them around 230 MTr/mm2 by 2026. When viewed by this metric, Intel is really falling behind.

Intel has a 1.4nm process in the pipeline for ~2027. They just took delivery on their first high NA EUV machine in order to start working on it. Their gamble however is that they need to figure out DSA, a long storied technology that uses self-forming polymers to allow less light to sharply etch smaller features. If they figure out DSA, they will likely be ahead of TSMC. If not, it will just be more very expensive la…

DSA = Directed Self-Assembly

Re: TSMC unveils 1.6nm process technology with backside power delivery

#82

Post by dmix »

bmicraft wrote: post #47
tommiegannert wrote: post #26

Earlier quoted context omitted.

The problem is it sounds like something any engineer can understand without domain knowledge, but interpreting it that way is completely wrong. The worst kind of naming. Not just IKEA-style random names (and I say that as a Swede,) but reusing a standard, while not keeping to what the standard is normally used for, and what it previously meant even in this domain. N1.6 is much better for naming node processes. Or eve…

Normally? That "standard" hasn't been used "normally" for 20 years now. Arguably the new way is normal in every sense of the word

Do you think they'll be advertising 0.9nm in the future or switch it up at some point?

Re: TSMC unveils 1.6nm process technology with backside power delivery

#83

Post by blagie »

AdamN wrote: post #78
blagie wrote: post #35

Earlier quoted context omitted.

ELI5: ICs are manufactured on silicon disks called wafers. Discs have two sides, and traditionally, everything was done on top. We can now do power on the bottom. This makes things go faster and use less power: * Power wires are big (and can be a bit crude). The bigger the better. Signal wires are small and precise. Smaller is generally better. * Big wires, if near signal wires, can interfere with them working optima…

There's still the question though of why they didn't do this decades ago - seems very obvious that this layout is better. What changed that made it possible only now and not earlier?

My knowledge isn't current enough to offer more than speculation.

However, something like an 80286 didn't even require a heatsink, while my 80486 had a dinky heat sink similar to what you might find on a modern motherboard chipset. At the same time, on a micron node, wires were huge. A few special cases aside (DEC Alpha comes to mind), power distribution didn't require anything special beyond what you'd see on your signal wires, and wasn't a major part of the interconnect space.

Mapping out to 2024:

1) Signal wires became smaller than ever.

2) Power density is higher than ever, requiring bigger power wires.

So there is a growing disparity between the needs of the two.

At the same time, there is continued progress in figuring out how to make through-wafer vias more practical (see https://en.wikipedia.org/wiki/Three-dimensional_integrated_c...).

I suspect in 2000, this would have been basically restricted to $$$$ military-grade special processes and similar types of very expensive applications. In 2024, this can be practically done for consumer devices. As costs go down, and utility goes up, at some point, the two cross, leading to practical devices.

I suspect a lot of this is driven by progress in imagers. There, the gains are huge. You want a top wafer which is as close as possible to 100% sensor, but you need non-sensor area if you want any kind of realtime processing, full frame readout (e.g. avoiding rolling shutter), or rapid readout (e.g. high framerate). The first time I saw 3D IC technology in mainstream consumer use were prosumer-/professional-grade Sony cameras.

I have strong fundamentals, but again, I stopped following this closely maybe 15 years ago, so much of the above is speculative.

Re: TSMC unveils 1.6nm process technology with backside power delivery

#84

Post by Tempest1981 »

bayindirh wrote: post #3
tvbv wrote: post #2

could someone ELi5 the backside power delivery please ?

Signal wires and power wires are not routed together, but separately. As a result, transistors are sandwiched between two wiring stacks. Resulting in lower noise, but makes heat removal a bit harder AFAICS. See the image at: https://www.custompc.com/wp-content/sites/custompc/2023/06/I...

How many power layers are there? Or how do the power "wires" cross over each other?

Are they sparse, like wires? Or solid, like the ground plane of a PCB? Are there "burried vias"?

Re: TSMC unveils 1.6nm process technology with backside power delivery

#85

Post by Rinzler89 »

saganus wrote: post #69
Workaccount2 wrote: post #63

Earlier quoted context omitted.

Intel has a 1.4nm process in the pipeline for ~2027. They just took delivery on their first high NA EUV machine in order to start working on it. Their gamble however is that they need to figure out DSA, a long storied technology that uses self-forming polymers to allow less light to sharply etch smaller features. If they figure out DSA, they will likely be ahead of TSMC. If not, it will just be more very expensive la…

Do you know the name of the company that produces the EUV machine? is it ASML? It is my understanding that only ASML had cracked the EUV litography, but if there's another company out there, that would be an interesting development to watch.

>It is my understanding that only ASML had cracked the EUV litography

Ackshually, EUV was cracked by Sandia Labs research in the US, with EUV light sources built by Cymer in the US. ASML was the only one allowed to license the tech and integrate it into their steppers after they bough Cymer in 2013. Hence why US has veto rights to whom Dutch based ASML can sell their EUV steppers to, as in not to China, despite ow much ASML shareholders would like that extra Chinese money.

Re: TSMC unveils 1.6nm process technology with backside power delivery

#86

Post by yau8edq12i »

misja111 wrote: post #72
blackoil wrote: post #20

Earlier quoted context omitted.

Number represents transistor density. 2nm has ~twice the density of 4nm. If you ignore nm as unit of distance it makes sense.

Nope that's what it meant a long time ago. Nowadays, the nm number represents the smallest possible element on the chip, typically the gate length, which is smaller than the size of a transistor. This means that when different manufacturers use a different transistor design, their 'nm' process could be the same but their transistor density different.

No, it's not even related to gate length or any kind of physical feature anymore. It's a purely marketing term. A "3 nm" node has a gate length around 16-18 nm.

Re: TSMC unveils 1.6nm process technology with backside power delivery

#87

Post by 7thpower »

ReptileMan wrote: post #65
futureshock wrote: post #59

Comments about the marketing driven nm measurements aside, this still looks like another solid advance for TSMC. They are already significantly ahead of Samsung and Intel on transistor density. TSMC is at 197 MTr/mm2 wile Samsung is at 150 MTr/mm2 and Intel is at 123 MTr/mm2. This 1.6nm process will put them around 230 MTr/mm2 by 2026. When viewed by this metric, Intel is really falling behind.

Not understanding chip design - but is it possible to get more computational bang with less transistors - are there some optimizations to be had? Better design that could compensate for bigger nodes?

Yes, generally one of the trends has been movement toward specialized coprocessors/accelerators. This was happening before the recent AI push and has picked up steam.

If you think of an SOC, the chip in your phone, more and more of the real estate is being dedicated to specialized compute (AI accelerators, GPUs, etc. vs general purpose compute (CPU).

At the enterprise scale, one of the big arguments NVIDIA has been making, beyond their value in the AI market, has been the value of moving massive, resource intense workloads from CPU to more specialized GPU acceleration. In return for the investment to move their workload, customers can get a massive increase in performance per watt/dollar.

There are some other factors at play in that example, and it may not always be true that the transistors/mm^2 is always lower, but I think it illustrates the overall point.

Re: TSMC unveils 1.6nm process technology with backside power delivery

#89

Post by dev1ycan »

Workaccount2 wrote: post #63
futureshock wrote: post #59

Comments about the marketing driven nm measurements aside, this still looks like another solid advance for TSMC. They are already significantly ahead of Samsung and Intel on transistor density. TSMC is at 197 MTr/mm2 wile Samsung is at 150 MTr/mm2 and Intel is at 123 MTr/mm2. This 1.6nm process will put them around 230 MTr/mm2 by 2026. When viewed by this metric, Intel is really falling behind.

Intel has a 1.4nm process in the pipeline for ~2027. They just took delivery on their first high NA EUV machine in order to start working on it. Their gamble however is that they need to figure out DSA, a long storied technology that uses self-forming polymers to allow less light to sharply etch smaller features. If they figure out DSA, they will likely be ahead of TSMC. If not, it will just be more very expensive la…

Intel says a lot of things but until they put them out in the field I don't believe a word they say

Re: TSMC unveils 1.6nm process technology with backside power delivery

#90

Post by bmicraft »

dmix wrote: post #82
bmicraft wrote: post #47

Earlier quoted context omitted.

Normally? That "standard" hasn't been used "normally" for 20 years now. Arguably the new way is normal in every sense of the word

Do you think they'll be advertising 0.9nm in the future or switch it up at some point?

Intel has already switched to Ångström for the most part
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