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TSMC unveils 1.6nm process technology with backside power delivery

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Re: TSMC unveils 1.6nm process technology with backside power delivery

#41

Post by thsksbd »

api wrote: post #27
blagie wrote: post #23

Earlier quoted context omitted.

Because it lost meaning somewhere between a micron and 100nm. From roughly the 1960s through the end of the 1990s, the number meant printed gate lengths or half-pitch (which were identical). At some point, companies started using "equivalences" which became increasingly detached from reality. If my 50nm node had better performance than your 30nm node because I have FinFETs or SOI or whatever, shouldn't I call mine 30…

The same thing happened with chip frequency around the end of the 1990s. Chip frequencies stagnated (end of Dennard scaling if I remember correctly) giving the impression that single threaded performance had stagnated, but since then chip makers have used increasing data and instruction parallelism to squeeze even more apparent single threaded performance out of chips. A 3ghz chip today is usually way faster on avera…

"For fab processes we should just switch to transistor density."

Indeed

May I propose transistor density divided by the (ergodic) average transistor switching power?

Re: TSMC unveils 1.6nm process technology with backside power delivery

#42

Post by antisthenes »

api wrote: post #27
blagie wrote: post #23

Earlier quoted context omitted.

Because it lost meaning somewhere between a micron and 100nm. From roughly the 1960s through the end of the 1990s, the number meant printed gate lengths or half-pitch (which were identical). At some point, companies started using "equivalences" which became increasingly detached from reality. If my 50nm node had better performance than your 30nm node because I have FinFETs or SOI or whatever, shouldn't I call mine 30…

The same thing happened with chip frequency around the end of the 1990s. Chip frequencies stagnated (end of Dennard scaling if I remember correctly) giving the impression that single threaded performance had stagnated, but since then chip makers have used increasing data and instruction parallelism to squeeze even more apparent single threaded performance out of chips. A 3ghz chip today is usually way faster on avera…

> For fab processes we should just switch to transistor density.

The marketing departments of silicon companies are saving that as their ultimate weapon.

Re: TSMC unveils 1.6nm process technology with backside power delivery

#43

Post by brandall10 »

chmod775 wrote: post #17
s_dev wrote: post #12

Earlier quoted context omitted.

Why is it meaningless?

Because it's not measuring anything, except the tech generation. It conveys about as much information as "iPhone 14".

While it may be divorced from any particular measurement, doesn't it give an approximation of increased density?

Re: TSMC unveils 1.6nm process technology with backside power delivery

#44

Post by magicalhippo »

gtirloni wrote: post #29

> This technology is tailored specifically for AI and HPC processors that tend to have both complex signal wiring and dense power delivery networks Uh?

I imagine it's because AI and HPC processors are typically utilized much more fully than your regular desktop processor.

A typical desktop CPU is designed to execute very varied and branch-heavy code. As such they have a lot of cache and a lot of logic transistors sitting idle at any given time, either waiting for memory or because the code is adding not multiplying for example. You can see that in the die shots like this[1] for example. I imagine the caches are relatively regular and uniform and as such as less complex signal wiring, and idle transistors means lower power requirements.

AI and HPC processors are more stream-oriented, and as such contain relatively small cachees and a lot of highly-utilized logic transistors. Compare the desktop CPU with the NVIDIA A100[2] for example. Thus you got both complex wiring, all those execution units needs to be able to very quickly access the register file, and due to the stream-oriented nature one can fully utilize most of the chip so a more complex power delivery network is required.

edit: Power delivery tracks can affect signal tracks due to parasitic coupling if they're close enough, potentially causing signals to be misinterpreted by the recipient if power usage fluctuates which it will do during normal operation (if say an execution unit goes from being idle to working on an instruction, or vice versa). Thus it can be challenging to fit both power and signal tracks in close proximity.

[1]: https://wccftech.com/amd-ryzen-5000-zen-3-vermeer-undressed-...

[2]: https://www.tomshardware.com/news/nvidia-ampere-A100-gpu-7nm

Re: TSMC unveils 1.6nm process technology with backside power delivery

#45

Post by phkahler »

thsksbd wrote: post #40
__alexs wrote: post #38

Earlier quoted context omitted.

TSMC N5 is indeed about 30% more Transistors/mm2 than N7 as you might expect so seems reasonably meaningful?

1.6 nm is 16 A. If they continue the BS for much longer, the "feature size" will be smaller than the lattice of Si.

And it's not that much better than the previous 2nm node, so it seems like the number is just meant to be smaller than Intel 18A. I wish Intel in the switch to "A" would have at least returned to a physically meaningful measure. Then just maybe the industry could agree to use that for a while. Like 180A or whatever it needed to be - maybe just the smallest metal pitch or something.

Re: TSMC unveils 1.6nm process technology with backside power delivery

#46

Post by __alexs »

thsksbd wrote: post #40
__alexs wrote: post #38

Earlier quoted context omitted.

TSMC N5 is indeed about 30% more Transistors/mm2 than N7 as you might expect so seems reasonably meaningful?

1.6 nm is 16 A. If they continue the BS for much longer, the "feature size" will be smaller than the lattice of Si.

You're the one calling it a feature size, not TSMC.

Re: TSMC unveils 1.6nm process technology with backside power delivery

#47

Post by bmicraft »

tommiegannert wrote: post #26
gwervc wrote: post #18

Earlier quoted context omitted.

It's at least more easily understandable (lower is newer) than the average tech product naming scheme, especially those by Microsoft.

The problem is it sounds like something any engineer can understand without domain knowledge, but interpreting it that way is completely wrong. The worst kind of naming. Not just IKEA-style random names (and I say that as a Swede,) but reusing a standard, while not keeping to what the standard is normally used for, and what it previously meant even in this domain. N1.6 is much better for naming node processes. Or eve…

Normally? That "standard" hasn't been used "normally" for 20 years now. Arguably the new way is normal in every sense of the word

Re: TSMC unveils 1.6nm process technology with backside power delivery

#48

Post by _heimdall »

blackoil wrote: post #20
Havoc wrote: post #8

>1.6nm Gotta love how we now have fractions of a near meaningless metric.

Number represents transistor density. 2nm has ~twice the density of 4nm. If you ignore nm as unit of distance it makes sense.

They're using the wrong units if we need to consider the nanometer as something other than a measure of distance.

Re: TSMC unveils 1.6nm process technology with backside power delivery

#49

Post by consp »

blagie wrote: post #35
tvbv wrote: post #2

could someone ELi5 the backside power delivery please ?

ELI5: ICs are manufactured on silicon disks called wafers. Discs have two sides, and traditionally, everything was done on top. We can now do power on the bottom. This makes things go faster and use less power: * Power wires are big (and can be a bit crude). The bigger the better. Signal wires are small and precise. Smaller is generally better. * Big wires, if near signal wires, can interfere with them working optima…

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