>1.6nm Gotta love how we now have fractions of a near meaningless metric.
I hear it also has many megahertz.
TSMC unveils 1.6nm process technology with backside power delivery
61–70 of 209 posts
Re: TSMC unveils 1.6nm process technology with backside power delivery
#62Earlier quoted context omitted.
Half your wires deliver power, half deliver signal. So if you do both on the same side, you need twice the density of wires. If you split the delivery into two parts, you get double the density without needing to make things smaller.
This isn't quite right. Big wires (ideally entire planes) deliver power. Small wires deliver signal. Half and half isn't the right split, and you don't want to make power wires smaller. The very different requirements of the two is where a lot of the gains come in.
It is going to get even a bit more interesting when you consider power gaters and virtual power supplies. Now the real power will be on the back side and the virtual power will be on the front side. Fun time for power analysis.
Re: TSMC unveils 1.6nm process technology with backside power delivery
#63Comments about the marketing driven nm measurements aside, this still looks like another solid advance for TSMC. They are already significantly ahead of Samsung and Intel on transistor density. TSMC is at 197 MTr/mm2 wile Samsung is at 150 MTr/mm2 and Intel is at 123 MTr/mm2. This 1.6nm process will put them around 230 MTr/mm2 by 2026. When viewed by this metric, Intel is really falling behind.
Intel has a 1.4nm process in the pipeline for ~2027. They just took delivery on their first high NA EUV machine in order to start working on it.
Their gamble however is that they need to figure out DSA, a long storied technology that uses self-forming polymers to allow less light to sharply etch smaller features.
If they figure out DSA, they will likely be ahead of TSMC. If not, it will just be more very expensive languishing.
Re: TSMC unveils 1.6nm process technology with backside power delivery
#64A16 in 2027 vs Intel's 18A in full swing by 2026 feels like a miss on TMSCs behalf. This looks like an open door for fabless companies to try Intel's foundry service.
Intel hasn't got a great track record in recent history. Really hoping they can hit their timeline though.
Re: TSMC unveils 1.6nm process technology with backside power delivery
#65Comments about the marketing driven nm measurements aside, this still looks like another solid advance for TSMC. They are already significantly ahead of Samsung and Intel on transistor density. TSMC is at 197 MTr/mm2 wile Samsung is at 150 MTr/mm2 and Intel is at 123 MTr/mm2. This 1.6nm process will put them around 230 MTr/mm2 by 2026. When viewed by this metric, Intel is really falling behind.
Not understanding chip design - but is it possible to get more computational bang with less transistors - are there some optimizations to be had? Better design that could compensate for bigger nodes?
Re: TSMC unveils 1.6nm process technology with backside power delivery
#66Earlier quoted context omitted.
the pics go to 404
thanks, I've fixed them btw, you appear to be shadow banned, probably on account of being downvoted for making short comments like "good" or "I don't get it" Short & simple responses may be adequate at times, but usually people will view it as not adding anything Perhaps reviewing guidelines https://news.ycombinator.com/newsguidelines.html will give an idea of the ideal being yearned for (granted, it's an ideal). In…
How can you tell someone is shadowbanned?
Re: TSMC unveils 1.6nm process technology with backside power delivery
#67Comments about the marketing driven nm measurements aside, this still looks like another solid advance for TSMC. They are already significantly ahead of Samsung and Intel on transistor density. TSMC is at 197 MTr/mm2 wile Samsung is at 150 MTr/mm2 and Intel is at 123 MTr/mm2. This 1.6nm process will put them around 230 MTr/mm2 by 2026. When viewed by this metric, Intel is really falling behind.
Not understanding chip design - but is it possible to get more computational bang with less transistors - are there some optimizations to be had? Better design that could compensate for bigger nodes?
Such optimisation would apply equally to the more dense processes, though.
Re: TSMC unveils 1.6nm process technology with backside power delivery
#68Comments about the marketing driven nm measurements aside, this still looks like another solid advance for TSMC. They are already significantly ahead of Samsung and Intel on transistor density. TSMC is at 197 MTr/mm2 wile Samsung is at 150 MTr/mm2 and Intel is at 123 MTr/mm2. This 1.6nm process will put them around 230 MTr/mm2 by 2026. When viewed by this metric, Intel is really falling behind.
Not understanding chip design - but is it possible to get more computational bang with less transistors - are there some optimizations to be had? Better design that could compensate for bigger nodes?
In general, yes, but all the chip design companies have already invested a whole lot of time and engineering resources into squeezing as much as possible from each transistor. But those kinds of optimizations are certainly part of why we sometimes see new CPU generations released on the same node.
Re: TSMC unveils 1.6nm process technology with backside power delivery
#69Comments about the marketing driven nm measurements aside, this still looks like another solid advance for TSMC. They are already significantly ahead of Samsung and Intel on transistor density. TSMC is at 197 MTr/mm2 wile Samsung is at 150 MTr/mm2 and Intel is at 123 MTr/mm2. This 1.6nm process will put them around 230 MTr/mm2 by 2026. When viewed by this metric, Intel is really falling behind.
Intel has a 1.4nm process in the pipeline for ~2027. They just took delivery on their first high NA EUV machine in order to start working on it. Their gamble however is that they need to figure out DSA, a long storied technology that uses self-forming polymers to allow less light to sharply etch smaller features. If they figure out DSA, they will likely be ahead of TSMC. If not, it will just be more very expensive la…
Do you know the name of the company that produces the EUV machine? is it ASML?
It is my understanding that only ASML had cracked the EUV litography, but if there's another company out there, that would be an interesting development to watch.