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TSMC unveils 1.6nm process technology with backside power delivery

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Re: TSMC unveils 1.6nm process technology with backside power delivery

#121

Post by EMCymatics »

ano-ther wrote: post #100
Rinzler89 wrote: post #85

Earlier quoted context omitted.

>It is my understanding that only ASML had cracked the EUV litography Ackshually , EUV was cracked by Sandia Labs research in the US, with EUV light sources built by Cymer in the US. ASML was the only one allowed to license the tech and integrate it into their steppers after they bough Cymer in 2013. Hence why US has veto rights to whom Dutch based ASML can sell their EUV steppers to, as in not to China, despite ow m…

More on the history here: https://www.asml.com/en/news/stories/2022/making-euv-lab-to-...

Thanks for the source. I'm glad Bell labs pounced on the opportunity.

Re: TSMC unveils 1.6nm process technology with backside power delivery

#122

Post by confused_boner »

Sysreq2 wrote: post #95
Workaccount2 wrote: post #63

Earlier quoted context omitted.

Intel has a 1.4nm process in the pipeline for ~2027. They just took delivery on their first high NA EUV machine in order to start working on it. Their gamble however is that they need to figure out DSA, a long storied technology that uses self-forming polymers to allow less light to sharply etch smaller features. If they figure out DSA, they will likely be ahead of TSMC. If not, it will just be more very expensive la…

The nomenclature for microchip manufacturing left reality a couple generations ago. Intel’s 14A process is not a true 14A half-pitch. It’s kind of like how they started naming CPUs off “performance equivalents” instead of using raw clock speed. And this isn’t just Intel. TSMC, Samsung, everyone is doing half-pitch equivalent naming now a days. This is the industry roadmap from 2022: https://irds.ieee.org/images/files…

would performance per watt be the right way to benchmark?

Re: TSMC unveils 1.6nm process technology with backside power delivery

#123

Post by tommiegannert »

bmicraft wrote: post #47
tommiegannert wrote: post #26

Earlier quoted context omitted.

The problem is it sounds like something any engineer can understand without domain knowledge, but interpreting it that way is completely wrong. The worst kind of naming. Not just IKEA-style random names (and I say that as a Swede,) but reusing a standard, while not keeping to what the standard is normally used for, and what it previously meant even in this domain. N1.6 is much better for naming node processes. Or eve…

Normally? That "standard" hasn't been used "normally" for 20 years now. Arguably the new way is normal in every sense of the word

Yes. By standard I mean that nanometers ("nm") is used to describe physical distances. That's it's normal use, understood by all engineers. That's also how it was born into the semiconductor domain. In that domain, it should have either stayed a description of physical distances, or been replaced.

They could invent codenames, or start using a better (physical) metric, if this one is no longer relevant.

Re: TSMC unveils 1.6nm process technology with backside power delivery

#124

Post by smolder »

rowanG077 wrote: post #114
futureshock wrote: post #59

Comments about the marketing driven nm measurements aside, this still looks like another solid advance for TSMC. They are already significantly ahead of Samsung and Intel on transistor density. TSMC is at 197 MTr/mm2 wile Samsung is at 150 MTr/mm2 and Intel is at 123 MTr/mm2. This 1.6nm process will put them around 230 MTr/mm2 by 2026. When viewed by this metric, Intel is really falling behind.

Are intel really just the best chip designers on the earth or why can they compete with such densities with AMD?

I'd say they haven't been very competitive with AMD in performance per watt/dollar in the ryzen era, specifically due to process advantage. (On CPU dies especially, with less advantage for AMDs I/O dies.) I'd agree they have done a good job advancing other aspects of their designs to close the gap, though.

Re: TSMC unveils 1.6nm process technology with backside power delivery

#125

Post by jjk166 »

ReptileMan wrote: post #65
futureshock wrote: post #59

Comments about the marketing driven nm measurements aside, this still looks like another solid advance for TSMC. They are already significantly ahead of Samsung and Intel on transistor density. TSMC is at 197 MTr/mm2 wile Samsung is at 150 MTr/mm2 and Intel is at 123 MTr/mm2. This 1.6nm process will put them around 230 MTr/mm2 by 2026. When viewed by this metric, Intel is really falling behind.

Not understanding chip design - but is it possible to get more computational bang with less transistors - are there some optimizations to be had? Better design that could compensate for bigger nodes?

The design optimization software for modern semiconductors is arguably the most advanced design software on earth with likely tens if not hundreds of millions of man-years put into it. It takes into account not only the complex physics that apply at the nano-scale but also the interplay of the various manufacturing steps and optimizes trillions of features. Every process change brings about new potential optimizations, so rather than compensating for bigger nodes it actually widens the gap further. By analogy, the jump from hatchet to scalpel in the hands a layman is far less than the jump from hatchet to scalpel for a skilled surgeon.

Re: TSMC unveils 1.6nm process technology with backside power delivery

#126

Post by nabla9 »

saganus wrote: post #69
Workaccount2 wrote: post #63

Earlier quoted context omitted.

Intel has a 1.4nm process in the pipeline for ~2027. They just took delivery on their first high NA EUV machine in order to start working on it. Their gamble however is that they need to figure out DSA, a long storied technology that uses self-forming polymers to allow less light to sharply etch smaller features. If they figure out DSA, they will likely be ahead of TSMC. If not, it will just be more very expensive la…

Do you know the name of the company that produces the EUV machine? is it ASML? It is my understanding that only ASML had cracked the EUV litography, but if there's another company out there, that would be an interesting development to watch.

Yes, and Intel was the first to install the first High-NA EUV machine from ASML, TWINSCAN EXE:5000 https://www.youtube.com/watch?v=3PCtf1ONYMU

ps. Intel used to own 15% of ASML in 2012, now they own less than 2%.

Re: TSMC unveils 1.6nm process technology with backside power delivery

#127

Post by oivey »

ano-ther wrote: post #100
Rinzler89 wrote: post #85

Earlier quoted context omitted.

>It is my understanding that only ASML had cracked the EUV litography Ackshually , EUV was cracked by Sandia Labs research in the US, with EUV light sources built by Cymer in the US. ASML was the only one allowed to license the tech and integrate it into their steppers after they bough Cymer in 2013. Hence why US has veto rights to whom Dutch based ASML can sell their EUV steppers to, as in not to China, despite ow m…

More on the history here: https://www.asml.com/en/news/stories/2022/making-euv-lab-to-...

Pretty cool story of the National Lab system and the closest thing the US has to “government scientists” massively shaping the future.

Re: TSMC unveils 1.6nm process technology with backside power delivery

#128

Post by saganus »

Rinzler89 wrote: post #85
saganus wrote: post #69

Earlier quoted context omitted.

Do you know the name of the company that produces the EUV machine? is it ASML? It is my understanding that only ASML had cracked the EUV litography, but if there's another company out there, that would be an interesting development to watch.

>It is my understanding that only ASML had cracked the EUV litography Ackshually , EUV was cracked by Sandia Labs research in the US, with EUV light sources built by Cymer in the US. ASML was the only one allowed to license the tech and integrate it into their steppers after they bough Cymer in 2013. Hence why US has veto rights to whom Dutch based ASML can sell their EUV steppers to, as in not to China, despite ow m…

Did not know that. Thanks

Re: TSMC unveils 1.6nm process technology with backside power delivery

#129

Post by audunw »

misja111 wrote: post #72
blackoil wrote: post #20

Earlier quoted context omitted.

Number represents transistor density. 2nm has ~twice the density of 4nm. If you ignore nm as unit of distance it makes sense.

Nope that's what it meant a long time ago. Nowadays, the nm number represents the smallest possible element on the chip, typically the gate length, which is smaller than the size of a transistor. This means that when different manufacturers use a different transistor design, their 'nm' process could be the same but their transistor density different.

You have it the wrong way around. The nm number used to mean minimum gate length. But when moving to FinFET and other transistor innovations that provided increased density, they decreases the “nm” number AS IF the increased transistor density came from shrinking gate length with a traditional planar transistor.

The nm has always been a very rough approximate proxy for transistor density. Nothing has really changed about how what the number implies.

I find it so weird how so many people on hacker is so hung up on the “nm” numbering. None of these people are designing standard cell libraries and those that actually design standard cell libraries never cared about what’s in the marketing material anyway.

Lowe number means higher transistor density in some ways, on some parts of the chip. That’s all

Re: TSMC unveils 1.6nm process technology with backside power delivery

#130

Post by futureshock »

confused_boner wrote: post #122
Sysreq2 wrote: post #95

Earlier quoted context omitted.

The nomenclature for microchip manufacturing left reality a couple generations ago. Intel’s 14A process is not a true 14A half-pitch. It’s kind of like how they started naming CPUs off “performance equivalents” instead of using raw clock speed. And this isn’t just Intel. TSMC, Samsung, everyone is doing half-pitch equivalent naming now a days. This is the industry roadmap from 2022: https://irds.ieee.org/images/files…

would performance per watt be the right way to benchmark?

Benchmarks are tricky because it all depends on workload and use case. If you are in a VR headset for example, it’s all about power envelope and GPU flops. If you are in a Desktop used for productivity it might be all about peak CPU performance.
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