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Chisel: Constructing Hardware in a Scala Embedded Language

chisel.eecs.berkeley.edu

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Re: Chisel: Constructing Hardware in a Scala Embedded Language

#41

Post by MootWoop »

nickpsecurity wrote: post #40
minthd wrote: post #34

Earlier quoted context omitted.

Still , Cx - lang is having a real hard time to find customers. So what's missing ?

That's part of what I'm trying to find out. To be fair, most open-source, high-level synthesis tools don't have a lot of customers. Even Chisel doesn't have near as many users as its successes deserve. That's common for ASIC or FPGA tools that aren't the big name. For now, my preliminary answer is that people: (a) just use Altera and Xilinx HLS tools for FPGA because they're cheap and work well with their products; (…

Matthieu, co-founder of Synflow here. Maybe I could help? Don't hesitate to send me an email!

Re: Chisel: Constructing Hardware in a Scala Embedded Language

#42

Post by stephenmm »

trsohmers wrote: post #32
stephenmm wrote: post #26

Earlier quoted context omitted.

I have some of the same concerns and would like to see someone from industry who has actually done it before I spend much more time on it. My additional question is then how did the academics do it? There are some tools that negate some/most of the need for gate sims but at my company we still do not ship without SOME gate sims.

@gluggymug You do realize you can do all of that simulation after you generate your verilog and put it through your RTL compiler?

It seems like you would need some sort of formal equivalence checking if that is the flow. Is there such a thing for Chisel?

Re: Chisel: Constructing Hardware in a Scala Embedded Language

#43

Post by gluggymug »

nickpsecurity wrote: post #39
gluggymug wrote: post #33

Earlier quoted context omitted.

I think maybe the HLS can get you a core design but then when you try to use it and integrate into an FPGA you will have to deal with the low level issues of registers and combinatorial logic. This is fine for the experienced HW person, but not for the beginner. In other words, the HLS is better for the experienced HW designer than the beginner even though it looks like its easy. Unfortunately there is no infrastruct…

Ok that all makes more sense. One of my potential flows was actually having the amateurs build lost of functionality (eg accelerators, device protocols) with HLS tools that a hardware engineer could finalize for FPGA. Would save on the rare labor. What do you think of that model vs exclusively leveraging HW people? Far as ASIC's, I'd just get HW people, haggle on the tools, use free one's if possible (see Qflow), and…

What do you think of that model vs exclusively leveraging HW people?

Sounds good.

Cheap fab I am not sure whether the costs make sense. Depends on the project I guess. I don't have a lot of experience with those manufacturing processes.

Re: Chisel: Constructing Hardware in a Scala Embedded Language

#44

Post by stephenmm »

gluggymug wrote: post #37
trsohmers wrote: post #31

Earlier quoted context omitted.

Of course we do all of our real tests on the generated verilog. (Note: There is a big difference between generated verilog, in the Chisel sense, and synthesized verilog, in the MyHDL sense). We use Chisel to write our RTL and do quick and dirty testing with our gold model, and if that matches up, we generate the verilog and do the "real" testing from that point. This whole flow is a iterative process that can happen…

Ok. If you do the majority of your testing on the generated Verilog, I am not sure what the point of the Chisel C++ cycle accurate simulator is. I thought that ran on the Chisel RTL. What simulator do you use to test the generated Verilog? And what language do you write the tests in?

Actually this is the area that I am most interested in. I am responsible for writing SystemC models of our designs so that firmware/software guys are able to work in parallel with RTL development but it takes me some time to create the models and get the timing reasonably equivalent (AT in SystemC speak) to the RTL. If I had a flow were the same source could generate cycle accurate models AND verilog this might be an acceptable answer and allow us to develop SW/FW much more quickly.

In my world even though hardware takes an extraordinarily long time the FW/SW is still the long poll in developing complex systems and anything that shortens the time to $$$ in the door we should probably be looking into.

Re: Chisel: Constructing Hardware in a Scala Embedded Language

#45

Post by szabba »

trsohmers wrote: post #7
bra-ket wrote: post #5

it's used by Rex: http://www.theplatform.net/2015/07/22/supercomputer-chip-sta...

Hey, CEO of REX here... would be happy to answer questions. P.S. We're hiring Chisel developers! If you don't know chisel, but want to learn and have RTL experience, we'd love to have you learn on the job! Check out our website: http://rexcomputing.com

I'm a layman, but the information on your website reminds be both of what GreenArrays are doing and of the 80's INMOS transputers. People might want to know how those compare with what you're working on.

Re: Chisel: Constructing Hardware in a Scala Embedded Language

#46

Post by gluggymug »

stephenmm wrote: post #44
gluggymug wrote: post #37

Earlier quoted context omitted.

Ok. If you do the majority of your testing on the generated Verilog, I am not sure what the point of the Chisel C++ cycle accurate simulator is. I thought that ran on the Chisel RTL. What simulator do you use to test the generated Verilog? And what language do you write the tests in?

Actually this is the area that I am most interested in. I am responsible for writing SystemC models of our designs so that firmware/software guys are able to work in parallel with RTL development but it takes me some time to create the models and get the timing reasonably equivalent (AT in SystemC speak) to the RTL. If I had a flow were the same source could generate cycle accurate models AND verilog this might be an…

That does sound like a good aspect of Chisel. How do they test that the Chisel RTL and the generated Verilog are equivalent though?

To me I would want a good verification environment that tests one against the other. Testing just via loading self-checking code into FW/SW is not enough. That's almost like SW verification. It assumes way too much is working correctly.

I am fantasizing if its possible to also write the Verification IP in Chisel AND convert that into a separate c++ library, then you can reuse it in a commercial Verilog RTL and gate-level simulator via a PLI.

That would serve many purposes and make Chisel useable in a generic flow.

Re: Chisel: Constructing Hardware in a Scala Embedded Language

#47

Post by cfelton »

trsohmers wrote: post #9
Skooma wrote: post #8

In my opinion, Chisel feels like "lets write Verilog with Scala syntax." I personally see MyHDL as a better approach as you can leverage existing libraries for generating code (i.e. use scipy to generate the coefficients for your FIR filter). One plus is Chisel generates C++ code for testing your design which is a huge speed increase versus simulating Verilog.

The biggest problem with MyHDL in my opinion (As someone using Chisel to make a commercial processor) is its (non existent) "real" simulation capabilities. If something is not cycle accurate (the way that Chisel's C++ simulator is), you can not really be positive of anything...and you don't want to get to physical design and find out you can't meet timing.

This is ridiculous, you can create cycle accurate (and bit accurate) descriptions in MyHDL. Anyone can verify this themselves by creating an RTL description in MyHDL, convert it to Verilog, and perform a Cosimulation. One can even Cosimulation with the back-annotated layout netlist and verify - yes cycle accurate.

Re: Chisel: Constructing Hardware in a Scala Embedded Language

#48

Post by cfelton »

trsohmers wrote: post #9
Skooma wrote: post #8

In my opinion, Chisel feels like "lets write Verilog with Scala syntax." I personally see MyHDL as a better approach as you can leverage existing libraries for generating code (i.e. use scipy to generate the coefficients for your FIR filter). One plus is Chisel generates C++ code for testing your design which is a huge speed increase versus simulating Verilog.

The biggest problem with MyHDL in my opinion (As someone using Chisel to make a commercial processor) is its (non existent) "real" simulation capabilities. If something is not cycle accurate (the way that Chisel's C++ simulator is), you can not really be positive of anything...and you don't want to get to physical design and find out you can't meet timing.

Here is some information on the speed of MyHDL, http://www.myhdl.org/documentation/performance.html.

Converting to yet another format can be a pain and potentially dangerous, if you are creating a commercial ASIC you need to guarantee each of these formats/representations are equivalent, if there is a discrepancy between the generated C++ and generated Verilog for implementation - oh boy.

Re: Chisel: Constructing Hardware in a Scala Embedded Language

#49

Post by cfelton »

trsohmers wrote: post #20
gluggymug wrote: post #15

Earlier quoted context omitted.

Okay this is getting weird. I just read your link so this is all from my first impressions. MyHDL is talking about co-simulation on the gate-level netlist. They do not recommend it. However they say MyHDL can do co-simulation on Verilog RTL. That will be cycle accurate I believe. As I understand it Chisel can't even do co simulation at all. Am I incorrect? Essentially once you translate your Chisel design to verilog…

Chisel doesn't require co simulation, as it is actually RTL in itself... it describes actual logic (registers and gates) instead of the functionality of the chip (as MyHDL does). Chisel being actually RTL makes it much easier for actual hardware engineers to use, but still allows for very powerful paramaterization that cuts down on total number of lines that have to be written. I would even say that it being embedded…

That is very dangerous not verifying, in some means, that each of the formats are functionally identical. One could skip the Cosimulation in MyHDL as well. This has nothing to do with the so called abstraction level of chisel.

Re: Chisel: Constructing Hardware in a Scala Embedded Language

#50

Post by cfelton »

trsohmers wrote: post #31
gluggymug wrote: post #25

Earlier quoted context omitted.

I've been skimming through MyHDL stuff. It does support RTL like Chisel supposedly. http://docs.myhdl.org/en/latest/manual/rtl.html So it should simulate RTL and give you cycle accurate waves. No gate level sim for either tool means you're dead meat which ever way you go, so I am not sure why I am even bothering to look at this stuff. The respective merits of each approach is somewhat pointless when crucial steps in…

Of course we do all of our real tests on the generated verilog. (Note: There is a big difference between generated verilog, in the Chisel sense, and synthesized verilog, in the MyHDL sense). We use Chisel to write our RTL and do quick and dirty testing with our gold model, and if that matches up, we generate the verilog and do the "real" testing from that point. This whole flow is a iterative process that can happen…

This is useless without any data: "big difference between the generated verilog". You would need an actual case study to confidently state these and as pointed out with programming languages this is difficult to do.
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