Chisel: Constructing Hardware in a Scala Embedded Language
chisel.eecs.berkeley.edu
Chisel: Constructing Hardware in a Scala Embedded Language
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Re: Chisel: Constructing Hardware in a Scala Embedded Language
#2They claim this language is highly parameterized. I wonder how much.
For example can you design a generic processor in such a way that everything will be parameterized?
Re: Chisel: Constructing Hardware in a Scala Embedded Language
#3They claim this language is highly parameterized. I wonder how much. For example can you design a generic processor in such a way that everything will be parameterized?
They use this language for RISC-V, if you look at the sources you can see the kind of things that can be parameterized.
Re: Chisel: Constructing Hardware in a Scala Embedded Language
#4I've been playing with this for the past few weeks. It's a lot of fun compared to Verilog or VHDL. The implementation is still young, though, and it's pretty easy to trigger an undecipherable crash. But I haven't had anything miscompile yet.
Re: Chisel: Constructing Hardware in a Scala Embedded Language
#5it's used by Rex: http://www.theplatform.net/2015/07/22/supercomputer-chip-sta...
Re: Chisel: Constructing Hardware in a Scala Embedded Language
#6I've been playing with this for the past few weeks. It's a lot of fun compared to Verilog or VHDL. The implementation is still young, though, and it's pretty easy to trigger an undecipherable crash. But I haven't had anything miscompile yet.
I'm trying to get the Amulet1 (Async/unclocked ARM from Manchester, back in the day) working as a test project. This, of course, requires Muller C-gate stuff. I'm having a bit of trouble getting it all to work out.
Have you seen any obvious techniques/methods for unclocked circuits that I am probably looking right past?
Re: Chisel: Constructing Hardware in a Scala Embedded Language
#7it's used by Rex: http://www.theplatform.net/2015/07/22/supercomputer-chip-sta...
Hey, CEO of REX here... would be happy to answer questions.
P.S. We're hiring Chisel developers! If you don't know chisel, but want to learn and have RTL experience, we'd love to have you learn on the job! Check out our website: http://rexcomputing.com
Re: Chisel: Constructing Hardware in a Scala Embedded Language
#8In my opinion, Chisel feels like "lets write Verilog with Scala syntax." I personally see MyHDL as a better approach as you can leverage existing libraries for generating code (i.e. use scipy to generate the coefficients for your FIR filter). One plus is Chisel generates C++ code for testing your design which is a huge speed increase versus simulating Verilog.
Re: Chisel: Constructing Hardware in a Scala Embedded Language
#9In my opinion, Chisel feels like "lets write Verilog with Scala syntax." I personally see MyHDL as a better approach as you can leverage existing libraries for generating code (i.e. use scipy to generate the coefficients for your FIR filter). One plus is Chisel generates C++ code for testing your design which is a huge speed increase versus simulating Verilog.
The biggest problem with MyHDL in my opinion (As someone using Chisel to make a commercial processor) is its (non existent) "real" simulation capabilities. If something is not cycle accurate (the way that Chisel's C++ simulator is), you can not really be positive of anything...and you don't want to get to physical design and find out you can't meet timing.
Re: Chisel: Constructing Hardware in a Scala Embedded Language
#10Chisel is a nice toolkit that proved itself in the Rocket processor. One of the more unusual uses of it was Chisel-Q for quantum computing:
http://www.cs.berkeley.edu/~kubitron/papers/qarc/pdf/Chisel-...
Chisel is pretty well-known in academic, hardware community. So, here's a few that you might have not heard of.
Caisson - language-based security meets HDL http://www.cs.ucsb.edu/~chong/papers/109-Caisson-pldi.pdf
SHard - a scheme to hardware compiler http://scheme2006.cs.uchicago.edu/05-saint-mleux.pdf
Cx-Lang - A statically-typed, c-like, HLL for hardware http://cx-lang.org/
Note: I'd love for some people familiar with ASIC or FPGA design to check out Cx-Lang to see if it's good for beginners getting results on FPGA's. The I.P. they sell is so cheap that it's either (a) crap or (b) the result of a productive, synthesis tool (Cx). Just like to know if it's a decent HLS tool compared to FPGA or EDA company offerings. Additional advantage that it's open so it can be reviewed for subversion if one is willing to invest the effort.