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Chisel: Constructing Hardware in a Scala Embedded Language

chisel.eecs.berkeley.edu

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Re: Chisel: Constructing Hardware in a Scala Embedded Language

#21

Post by stephenmm »

trsohmers wrote: post #7
bra-ket wrote: post #5

it's used by Rex: http://www.theplatform.net/2015/07/22/supercomputer-chip-sta...

Hey, CEO of REX here... would be happy to answer questions. P.S. We're hiring Chisel developers! If you don't know chisel, but want to learn and have RTL experience, we'd love to have you learn on the job! Check out our website: http://rexcomputing.com

Chisel is potentially a revolution in hardware design and I am following it intently but I have not heard of anyone creating an actual chip from a standard fab as of yet. I am trying to make an argument for trying this at my work but I think until we get some more feedback from people in industry it may be too risky of an endeavour. It would be great if you would be willing to share your experiences or know of some papers that would help me build an argument for trying it out.

Re: Chisel: Constructing Hardware in a Scala Embedded Language

#22

Post by nickpsecurity »

trsohmers wrote: post #18
gluggymug wrote: post #16

Earlier quoted context omitted.

I think it is a high level synthesis tool like a SystemC etc. My concern for a beginner would be how to get your high level design integrated into the FPGA. For a beginner, there are a lot of what-ifs that they are probably going to stumble on.

Chisel is not high level synthesis, which is one of the reasons why I love it. You are actually describing the circuit itself, with is what a hardware description language is supposed to do. While describing the function of a circuit like MyHDL and many other languages have tried to do it cute, they have never come close to a real engineer thinking of how to solve the problem with registers and combinational logic di…

Of course it's not. That's why real HW types use it and people like me don't. ;) One of my goals on HW security side is to bring synthesis to a level that non-HW people can use it for an OK solution. I found Cx when looking at the awesome Qflow method and tools.

Since you post a lot, what's your opinion on Cx as a HLS tool for programmers without expertise as HW engineers? And outside big EDA, what is your recommendation for lowest cost vs effectiveness HLS for those wanting to clean-slate their hardware or at least accelerate things on FPGA's?

Re: Chisel: Constructing Hardware in a Scala Embedded Language

#23

Post by trsohmers »

stephenmm wrote: post #21
trsohmers wrote: post #7

Earlier quoted context omitted.

Hey, CEO of REX here... would be happy to answer questions. P.S. We're hiring Chisel developers! If you don't know chisel, but want to learn and have RTL experience, we'd love to have you learn on the job! Check out our website: http://rexcomputing.com

Chisel is potentially a revolution in hardware design and I am following it intently but I have not heard of anyone creating an actual chip from a standard fab as of yet. I am trying to make an argument for trying this at my work but I think until we get some more feedback from people in industry it may be too risky of an endeavour. It would be great if you would be willing to share your experiences or know of some p…

UC Berkeley has taped out ~10-12 chips entirely designed using Chisel through the standard flow and fabed at TSMC (As low at 28nm) and all have functioned. My start up has had minimal problems with using Chisel and going through both Cadence and Synopsys tools (most if not all the problems were user error :P)

Once we get closer to having silicon in hand, I'd love to publish our experience as both a startup making a new processor in this day and age, along with using Chisel and other new tools.

Re: Chisel: Constructing Hardware in a Scala Embedded Language

#24

Post by stephenmm »

trsohmers wrote: post #7
bra-ket wrote: post #5

it's used by Rex: http://www.theplatform.net/2015/07/22/supercomputer-chip-sta...

Hey, CEO of REX here... would be happy to answer questions. P.S. We're hiring Chisel developers! If you don't know chisel, but want to learn and have RTL experience, we'd love to have you learn on the job! Check out our website: http://rexcomputing.com

So is the idea that the compiler would try and optimize it so that both code and data would be kept local in the scratchpad memory and if there was a scratchpad "miss" the cores would DMA the needed memory locations from DRAM to the scratchpad?

Re: Chisel: Constructing Hardware in a Scala Embedded Language

#25

Post by gluggymug »

trsohmers wrote: post #20
gluggymug wrote: post #15

Earlier quoted context omitted.

Okay this is getting weird. I just read your link so this is all from my first impressions. MyHDL is talking about co-simulation on the gate-level netlist. They do not recommend it. However they say MyHDL can do co-simulation on Verilog RTL. That will be cycle accurate I believe. As I understand it Chisel can't even do co simulation at all. Am I incorrect? Essentially once you translate your Chisel design to verilog…

Chisel doesn't require co simulation, as it is actually RTL in itself... it describes actual logic (registers and gates) instead of the functionality of the chip (as MyHDL does). Chisel being actually RTL makes it much easier for actual hardware engineers to use, but still allows for very powerful paramaterization that cuts down on total number of lines that have to be written. I would even say that it being embedded…

I've been skimming through MyHDL stuff. It does support RTL like Chisel supposedly.

http://docs.myhdl.org/en/latest/manual/rtl.html

So it should simulate RTL and give you cycle accurate waves.

No gate level sim for either tool means you're dead meat which ever way you go, so I am not sure why I am even bothering to look at this stuff.

The respective merits of each approach is somewhat pointless when crucial steps in the HW process are completely ignored.

And now you are saying you don't test on the generated Verilog from Chisel? That's no good. No one should just run tests in Chisel. You're delivering HW not Chisel code as far as I am concerned. That's a few huge steps more in the flow that need vigorous testing. Where is the quality control?

So much more logic is added to chips during/after synthesis these days and you have no way to get any of your tests running on that net list.

Re: Chisel: Constructing Hardware in a Scala Embedded Language

#26

Post by stephenmm »

gluggymug wrote: post #25
trsohmers wrote: post #20

Earlier quoted context omitted.

Chisel doesn't require co simulation, as it is actually RTL in itself... it describes actual logic (registers and gates) instead of the functionality of the chip (as MyHDL does). Chisel being actually RTL makes it much easier for actual hardware engineers to use, but still allows for very powerful paramaterization that cuts down on total number of lines that have to be written. I would even say that it being embedded…

I've been skimming through MyHDL stuff. It does support RTL like Chisel supposedly. http://docs.myhdl.org/en/latest/manual/rtl.html So it should simulate RTL and give you cycle accurate waves. No gate level sim for either tool means you're dead meat which ever way you go, so I am not sure why I am even bothering to look at this stuff. The respective merits of each approach is somewhat pointless when crucial steps in…

I have some of the same concerns and would like to see someone from industry who has actually done it before I spend much more time on it. My additional question is then how did the academics do it? There are some tools that negate some/most of the need for gate sims but at my company we still do not ship without SOME gate sims.

Re: Chisel: Constructing Hardware in a Scala Embedded Language

#27

Post by gluggymug »

trsohmers wrote: post #18
gluggymug wrote: post #16

Earlier quoted context omitted.

I think it is a high level synthesis tool like a SystemC etc. My concern for a beginner would be how to get your high level design integrated into the FPGA. For a beginner, there are a lot of what-ifs that they are probably going to stumble on.

Chisel is not high level synthesis, which is one of the reasons why I love it. You are actually describing the circuit itself, with is what a hardware description language is supposed to do. While describing the function of a circuit like MyHDL and many other languages have tried to do it cute, they have never come close to a real engineer thinking of how to solve the problem with registers and combinational logic di…

While describing the function of a circuit like MyHDL and many other languages have tried to do it cute, they have never come close to a real engineer

I agree with you on that. For a beginner I think a high level language is the wrong direction to go because it's taking them further away from the method of designing a HW solution. It's adding another layer of abstraction.

Re: Chisel: Constructing Hardware in a Scala Embedded Language

#28

Post by nickpsecurity »

gluggymug wrote: post #27
trsohmers wrote: post #18

Earlier quoted context omitted.

Chisel is not high level synthesis, which is one of the reasons why I love it. You are actually describing the circuit itself, with is what a hardware description language is supposed to do. While describing the function of a circuit like MyHDL and many other languages have tried to do it cute, they have never come close to a real engineer thinking of how to solve the problem with registers and combinational logic di…

While describing the function of a circuit like MyHDL and many other languages have tried to do it cute, they have never come close to a real engineer I agree with you on that. For a beginner I think a high level language is the wrong direction to go because it's taking them further away from the method of designing a HW solution. It's adding another layer of abstraction.

That's what people said about going to 3GL's. I'm glad, for my day-to-day computing, that most went in the other direction (pro 3GL's). Software people can't get the kind of results hardware people can while using HLS techniques. That's obvious. Yet, the existing research shows they should be able to get quite a bit of results with little knowledge of hardware. EDA tools actually solved most of the hard parts. Only thing that's lacking are tools to accomplish this and at prices most people can afford.

Two paths developed in parallel. One for those trying to boost their software with hardware generation. One for hardware designers trying to improve their own craft. And with the benefit that one's tools can integrate the other. Best of both worlds.

So, I look for both.

Re: Chisel: Constructing Hardware in a Scala Embedded Language

#29

Post by trsohmers »

stephenmm wrote: post #24
trsohmers wrote: post #7

Earlier quoted context omitted.

Hey, CEO of REX here... would be happy to answer questions. P.S. We're hiring Chisel developers! If you don't know chisel, but want to learn and have RTL experience, we'd love to have you learn on the job! Check out our website: http://rexcomputing.com

So is the idea that the compiler would try and optimize it so that both code and data would be kept local in the scratchpad memory and if there was a scratchpad "miss" the cores would DMA the needed memory locations from DRAM to the scratchpad?

DRAM, or preferably a closer core. The memory on chip is all physically addressed, and part of a flat global address space. The first 128KB of the address space is core 0's memory, then the next 128KB is core 1's, and so on to core 255. When a core accesses a memory region not in its own local scratchpad, it hops along the network on chip (with one cycle per hop) to get to the core which has the needed memory address. The compiler would try to keep the needed data by a core in that cores local scratchpad, or if it can't, as close as possible. Even in the worse case scenario where a core needs to access the memory in the opposite corner (Core 0 accessing core 255), it is still only 32 cycles to access it (less than the ~40 cycles it takes to access L3 cache on an Intel chip).

The NoC is also entirely non blocking... a router is able to read/write to its cores scratchpad and do a passthrough in the same cycle.

Re: Chisel: Constructing Hardware in a Scala Embedded Language

#30

Post by gluggymug »

stephenmm wrote: post #26
gluggymug wrote: post #25

Earlier quoted context omitted.

I've been skimming through MyHDL stuff. It does support RTL like Chisel supposedly. http://docs.myhdl.org/en/latest/manual/rtl.html So it should simulate RTL and give you cycle accurate waves. No gate level sim for either tool means you're dead meat which ever way you go, so I am not sure why I am even bothering to look at this stuff. The respective merits of each approach is somewhat pointless when crucial steps in…

I have some of the same concerns and would like to see someone from industry who has actually done it before I spend much more time on it. My additional question is then how did the academics do it? There are some tools that negate some/most of the need for gate sims but at my company we still do not ship without SOME gate sims.

how did the academics do it?

Tape out using these tools?

My guess is they skipped gate level and other stuff that I consider good quality (BISTs, DFT logic, power estimation etc). You either skip it or rewrite your tests in Verilog/VHDL/etc.

Static Timing Analysis etc. can only do a little of what's needed. You have to check your constraints are correct.

Academics don't know what they are doing. They probably never had to do a design flow for a real product or even touched a commercial tool. It's too expensive. That's why they make these other tools. And that's why these tools kinda suck at getting to a finished product.

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