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ISA showdown: Is ARM, x86, or MIPS intrinsically more power efficient?

extremetech.com

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Re: ISA showdown: Is ARM, x86, or MIPS intrinsically more power efficient?

#21

Post by rcthompson »

ajross wrote: post #20
userbinator wrote: post #16

ARM and x86 are rather close, but the real disappointment here is the MIPS Loongson, which is basically the "original RISC ISA". Unfortunately I've encountered a huge number of people, particularly academics, who still think (and teach) that MIPS or minor variants of it are the "best" ISAs and that one can easily make cheap, fast, and power-efficient processors based on it. Looking at the current state of things, it…

The Loongson is a 90nm part, the others are 32-45nm. No ISA is going to make up for a doubled transistor size. Really the notable thing to me isn't the ISA nonsense at all. It's how singular a success the Cortex A9 core is. It came at exactly the right moment in history and hit exactly the right sweet spot, being significantly beefier than the A8 yet only minimally more power-hungry. Krait has followed on pretty well…

Yeah, based on just the data in this article, I would see A9 as preferable to A15 for using as the CPU of a mobile device.

Re: ISA showdown: Is ARM, x86, or MIPS intrinsically more power efficient?

#22

Post by wsxcde »

kristianp wrote: post #9

"The ISA being RISC or CISC seems irrelevant.". I thought these were all RISC processors when you get past the instruction decoder.

Not really. Both Intel and AMD do weird non-RISCy things beyond the decode stage.

The original difference between RISC and CISC was that RISC eschewed arithmetic+memory-operations in the same instruction. Both Intel and AMD processors violate this commandment. Instead their decomposition of instructions into uops is based more on the more pragmatic notion of choosing uops that are easy to pipeline and execute out of order.

Re: ISA showdown: Is ARM, x86, or MIPS intrinsically more power efficient?

#23

Post by hayfield »

aortega wrote: post #13

ABI is too high level to have any effect in power.

You can have an impact on power consumption at a range of levels. From choosing appropriate algorithms, to switching to different data types, to changing compiler flags. Add together a few of these 'easy' 5-10% energy savings and you've just reduced your application's energy consumption by a third (OK, it's not quite that simple, but the principle stands).

A couple of citations: http://arxiv.org/pdf/1406.0117v1.pdf (algorithms / data types) http://arxiv.org/pdf/1303.6485.pdf (compiler flags)

Re: ISA showdown: Is ARM, x86, or MIPS intrinsically more power efficient?

#25

Post by hayfield »

0x0 wrote: post #3
hendrik42 wrote: post #2

What irks me is computing and comparing W/Mips for vastly different processors like 45W Intel and 5W ARM chips. That just isn't reasonable, as performance increase is very sublinear in power.

Also, running the i7 in 32bit mode can't possibly be showing the intel chip from its best side?

There are a few other things that could also impact results. Looking at the experimental design, there could be a good 25% uncertainty in the results because of how it's done at such a high level.

Rough up-to values for various things I can think of / see:

- 10% because they're using an OS rather than running binaries straight.

- 15% because GCC is odd and -O3 does even stranger things, particularly when it comes to energy.

- 15% because their benchmarks are large workloads rather than microbenchmarks that may better target the architecture rather than being huge lumps (would exacerbate GCC strangeness).

- 17% because they're measuring board rather than CPU power supply (the claim that SoC-based ARM development boards cannot have processor power isolated is questionable - I've seen Beagleboards with the CPU power supply isolated)

- 10% because they're measuring energy consumption at a low resolution (their equipment measures in Hz when there's kit that happily measures in kHz or MHz).

Of course, some of these will cancel, and others will be nowhere near as bad as stated. It also doesn't introduce order-of-magnitude changes to the conclusions, although a few of the 'Key Findings' may want questioning.

Re: ISA showdown: Is ARM, x86, or MIPS intrinsically more power efficient?

#26

Post by josephlord »

With ARM different companies can license the design and include different system components on the chip. With Intel you need to take a packaged chip provided by Intel. This can allow a system power and cost advantage compared to having multiple chips. It is however a licensing/business model issue rather than a fundamental ISA issue.

Re: ISA showdown: Is ARM, x86, or MIPS intrinsically more power efficient?

#28

Post by sharpneli »

wmf wrote: post #12
kristianp wrote: post #9

"The ISA being RISC or CISC seems irrelevant.". I thought these were all RISC processors when you get past the instruction decoder.

Which still leaves the question of the cost of the instruction decoder.

It's a balancing act.

Power consumption by the instruction decoder vs the power consumption of additional cache&memory bandwidth.

It's amusing that despite the complaints towards X86 in the 90's nowadays it's actually a really good instruction packing format (though it became really sensible only after AMD64).

Re: ISA showdown: Is ARM, x86, or MIPS intrinsically more power efficient?

#29

Post by renox »

userbinator wrote: post #16

ARM and x86 are rather close, but the real disappointment here is the MIPS Loongson, which is basically the "original RISC ISA". Unfortunately I've encountered a huge number of people, particularly academics, who still think (and teach) that MIPS or minor variants of it are the "best" ISAs and that one can easily make cheap, fast, and power-efficient processors based on it. Looking at the current state of things, it…

> but all MIPS instructions are 4 bytes.

Like ARM, MIPS has also 16 bit extensions, two in fact: MIPS16 and microMIPS.

> [cut] thus I believe small variable-length encodings (like x86) are ultimately better since they allow for better utilisation of cache

I disagree: mixed 16/32 bit RISCs ISA have nearly the same code density as x86 and are far simpler to decode.

So beside software compatibility (the killer feature) (well except for Intel of course), the x86 ISA has NO advantage.

Re: ISA showdown: Is ARM, x86, or MIPS intrinsically more power efficient?

#30

Post by MrBuddyCasino »

userbinator wrote: post #16

ARM and x86 are rather close, but the real disappointment here is the MIPS Loongson, which is basically the "original RISC ISA". Unfortunately I've encountered a huge number of people, particularly academics, who still think (and teach) that MIPS or minor variants of it are the "best" ISAs and that one can easily make cheap, fast, and power-efficient processors based on it. Looking at the current state of things, it…

So the MIPS ISA is considered to be 'pure' RISC?

My rule of thumb: if something is conceptually "pure" instead of a complicated, carefully balanced mix of grey, its usually not worth considering.

I found this to be true for programming languages, ISAs, politics etc.

It is interesting how purity has a very strong allure - maybe our brains are naturally drawn to a reduced state of complexity, and thus energy consumption?

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