ISA showdown: Is ARM, x86, or MIPS intrinsically more power efficient?

Which still leaves the question of the cost of the instruction decoder.

Normalization is nice for a mental exercise, but I cannot buy a normalized phone with a normalized i7 that fits in my normalized pocket. Engineering is the art of trade-offs and the i7 has traded off size and power to achieve speed. That is great when you have an i7-scale size and power budget, but if the i7 exceeds your power or size budget it is a non-starter regardless of how efficient (when normalized) it is. Full stop.

The implicit argument of the paper is that Intel could produce a direct size+power+speed replacement for a phone-scale ARM processor, they just need to dial the knobs to small+small+slower. The counter argument is that they have tried but not come close. The Atom line is roughly comparable with respect to speed, but size and power are a problem. The Galileo processor is roughly comparable with respect to power and size but speed is horribly lacking.

ARM and x86 are rather close, but the real disappointment here is the MIPS Loongson, which is basically the "original RISC ISA". Unfortunately I've encountered a huge number of people, particularly academics, who still think (and teach) that MIPS or minor variants of it are the "best" ISAs and that one can easily make cheap, fast, and power-efficient processors based on it. Looking at the current state of things, it seems the only thing MIPS has succeeded in is being cheap and pedagogical.

I think instruction density has quite some significance here too - x86 opcodes vary between 1 and 15 bytes with 2-3 being average and ARM has Thumb mode where instructions are either 2 or 4 bytes, but all MIPS instructions are 4 bytes. It also has twice as much L1 as most of the ARM and x86 processors, which apparently didn't help it much. Cache consumes power too, and thus I believe small variable-length encodings (like x86) are ultimately better since they allow for better utilisation of cache; the extra complexity in the decoder to handle this, which basically amounts to a few barrel shifters, is almost nothing in comparison to the area and power that more cache would need.

The entire reason CISC architectures emphasized complex multi-cycle instruction execution is because memory accesses were orders of magnitude slower than the processor and data storage was extremely limited.

When considering cache, these points are all true again. There's a common belief about optimising for x86 to avoid the smaller but slower "CISC" instructions, but in situations like tight loops, an instruction that's 2-3x slower individually can be better than the faster longer one(s) if it means the difference between code and data staying in cache or a 10x+ slowdown from a cache miss somewhere else. Especially on an OoO/superscalar design where the slower instruction can be executed in parallel with other nondependent ones. (Intel/AMD's focus on speeding up these small CISC instructions - which they have done - is possibly one of the reasons why x86 performance continues to improve.)

Unless they carefully considered issues such as memory timing, or actually ran all the CPUs at 1GHz, just scaling results by clock frequency will make the x86s look worse and the ARMs better, because the x86s have a bigger gap between core and memory speed. Anyone who has experience with PC overclocking will know this - increasing the core clock by e.g. 25% will not make any benchmark (except maybe the most trivial of microbenchmarks) result improve by that same amount, and the same goes for the other direction: A 3.4GHz i7 run at 1GHz will not be 3.4x slower. On the other hand (no pun intended), the ARMs have a native frequency closer to 1GHz and scaling their results will not introduce as much error.

The Loongson is a 90nm part, the others are 32-45nm. No ISA is going to make up for a doubled transistor size.

Really the notable thing to me isn't the ISA nonsense at all. It's how singular a success the Cortex A9 core is. It came at exactly the right moment in history and hit exactly the right sweet spot, being significantly beefier than the A8 yet only minimally more power-hungry. Krait has followed on pretty well, but the A15 can almost be considered a failure at this point.