ISA showdown: Is ARM, x86, or MIPS intrinsically more power efficient?
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Re: ISA showdown: Is ARM, x86, or MIPS intrinsically more power efficient?
#2What irks me is computing and comparing W/Mips for vastly different processors like 45W Intel and 5W ARM chips. That just isn't reasonable, as performance increase is very sublinear in power.
Re: ISA showdown: Is ARM, x86, or MIPS intrinsically more power efficient?
#3What irks me is computing and comparing W/Mips for vastly different processors like 45W Intel and 5W ARM chips. That just isn't reasonable, as performance increase is very sublinear in power.
Also, running the i7 in 32bit mode can't possibly be showing the intel chip from its best side?
Re: ISA showdown: Is ARM, x86, or MIPS intrinsically more power efficient?
#4What irks me is computing and comparing W/Mips for vastly different processors like 45W Intel and 5W ARM chips. That just isn't reasonable, as performance increase is very sublinear in power.
Also, running the i7 in 32bit mode can't possibly be showing the intel chip from its best side?
Did anyone find a reasonably prominent link to the source?
It seems to me as if this article is mostly linkbait simply by reason of it failing to provide anything more than vague phrases about the source: "This paper is an updated version of one I’ve referenced in previous stories, ... the team from the University of Wisconsin"
Half-baked studies frequently attempt to shout down the real hard science.
Re: ISA showdown: Is ARM, x86, or MIPS intrinsically more power efficient?
#5Link to the study referenced by the article:
http://research.cs.wisc.edu/vertical/papers/2013/isa-power-s...
Re: ISA showdown: Is ARM, x86, or MIPS intrinsically more power efficient?
#6Earlier quoted context omitted.
Also, running the i7 in 32bit mode can't possibly be showing the intel chip from its best side?
Did anyone find a reasonably prominent link to the source? It seems to me as if this article is mostly linkbait simply by reason of it failing to provide anything more than vague phrases about the source: "This paper is an updated version of one I’ve referenced in previous stories, ... the team from the University of Wisconsin" Half-baked studies frequently attempt to shout down the real hard science.
Think we have the answer in the source article's abstract,
" Our methodical investigation demonstrates the role of ISA in modern microprocessors’ performance and energy efficiency. We find that ARM and x86 processors are simply engineering design points optimized for different levels of performance, and there is nothing fundamentally more energy efficient in one ISA class or the other. The ISA being RISC or CISC seems irrelevant."
http://research.cs.wisc.edu/vertical/papers/2013/isa-power-s...
Re: ISA showdown: Is ARM, x86, or MIPS intrinsically more power efficient?
#7What irks me is computing and comparing W/Mips for vastly different processors like 45W Intel and 5W ARM chips. That just isn't reasonable, as performance increase is very sublinear in power.
Also, running the i7 in 32bit mode can't possibly be showing the intel chip from its best side?
[deleted]
Re: ISA showdown: Is ARM, x86, or MIPS intrinsically more power efficient?
#8This is not a half baked study. The right comparison is being made, namely performance versus energy. Further, they attempt normalized comparisons, here quoting:
To factor out the impact of technology, present technology-independent power by scaling all processors to 45nm and normalizing the frequency to 1 GHz.
Re: ISA showdown: Is ARM, x86, or MIPS intrinsically more power efficient?
#9"The ISA being RISC or CISC seems irrelevant.".
I thought these were all RISC processors when you get past the instruction decoder.
Re: ISA showdown: Is ARM, x86, or MIPS intrinsically more power efficient?
#10The one argument I can make is that MIPS is too simple. But I would only make this claim on the simplest of in-order single or dual issue implementations. Think of a memcpy loop: 32-bit ARM and PowerPC can update the pointers as a side effect of the load and store instructions, but MIPS can not. You could make similar arguments in favour of ARM's thumb instruction set (more work done per 32-bits of instruction loaded with low decoding overhead vs. x86).
For implementations more advanced than this... I don't think you can make any such claim based on ISA. x86 may be at a slight disadvantage due to decoding, but that's about it.