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RISC-V: They Should Have Known Better

dmitry.gr

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Re: RISC-V: They Should Have Known Better

#91

Earlier quoted context omitted.

You don't need to probe what hardware you're running on because you know being the manufacturer. The code is bespoke for your solution and nothing more. No foreign code is going to run on it. Different problems require different solutions. An electric blanket doesn't need a barrel shifter for multiplication or even floating point hardware. The ISA can change depending on what's needed to solve a particular problem, n…

I'm not an embedded programmer myself, but from what I've heard... it's actually a pretty big assumption that the software people know what model hardware they're running on. Especially consider the possibility that a product manager decides to swap out the core for a different core to save 5¢ on the BOM. Does the product manager know to ask if the two cores follow the same RISC-V profile? Do the software programmers…

That doesn't really happen in the embedded space.

Even if the core was supported just fine, all of the IO mux stuff is pretty much guaranteed to be different even with the same chip in a different package.

You're looking at explicit support for each chip.

Re: RISC-V: They Should Have Known Better

#92
post #55

Why is he complaining about everything being optional in RISC-V? Isn't that the whole idea of RISC-V? The market can sort it out for themselves. RISC-V is already dominant in the MCU space despite its flaws, and many of them will be solved in due time. Most MCUs are used for dead-simple solutions, like electric blankets and microwaves with segment displays or LEDs. Whether their interrupts are handled in 44 or 22 cyc…

> "RISC-V is already dominant in the MCU space[...]" Where are you getting the idea that RISC-V is dominant? As someone who works in this space, that doesn't jive with my experience or the sources I've seen.[1] 32-bit microcontrollers only recently achieved a majority market share for gosh sakes! RISC-V is claiming that they have achieved 25% market share across selected segments, but they're still behind ARM (and x8…

It's used widely in Chinese stuff (which is basically everything) so in terms of volume it's probably already dominant.

In terms of dollar volume ARM is still the leader, especially for higher-end (application level MCUs) stuff. RISC-V MCUs with MMUs or MPUs are scarce at the moment.

Re: RISC-V: They Should Have Known Better

#93
post #45

Earlier quoted context omitted.

[flagged]

Both of your post are actual ad hominem towards OP. In the first, you just said they didn't know how software is developed, without elaborating. With this in mind, their reply is less of an ad hominem and more of an inquiry. In the next, you accuse them of having a fragile ego and being a kid. Not very insightful.

[flagged]

Re: RISC-V: They Should Have Known Better

#94
post #35

Earlier quoted context omitted.

> The market can sort it out for themselves Because nobody will write software for 300 unique hardware variations of a platform that have inconsistent capabilities. Consistency is one of the reasons why x86-64 with extensions like like SSE, AVX2 etc is popular.

Noone uses an 8051 because it's elegant. Billions are still still sold every year because no matter if you learned it in the 70s or last week and no matter who made it, the basics are exactly alike. Software matters; ISAs don't.

Every time I've seen someone use an 8051 in the past twenty years, it's had new, bespoke software written for it. They were more used because they were a known quantity with the patents obviously dead rather than support for existing codebases.

Re: RISC-V: They Should Have Known Better

#95

Earlier quoted context omitted.

> The market can sort it out for themselves Because nobody will write software for 300 unique hardware variations of a platform that have inconsistent capabilities. Consistency is one of the reasons why x86-64 with extensions like like SSE, AVX2 etc is popular.

I believe the market will standardize on certain extensions for specific solutions. No one is going to make a mobile phone with only RV32I, for example.

Yeah, that's the point of the profiles. A curated set of extensions for common use cases like application cores for generic software to target.

Re: RISC-V: They Should Have Known Better

#96
post #28

Earlier quoted context omitted.

I think MIPS is a great example, and even there I don't think there's the bizarre bifurcation of ISA options RISC-V brings to the table. As a fellow olderster, I can't help but think that after almost 50 years of "ISA X is sooooo much better than x86 it's obvious ISA X is the future and x86 will be dead Real Soon Now (for whatever todays version of x86 is)" I can only shake my head ruefully and say "ping me when that…

x86 chips don't truly exist anymore. They only use it as a compressed ISA for a more capable internal representation that can be freely updated at any time.

This is a load of bullshit that largely exists as copium to explain how x86 did the impossible and made a superscalar CISC processor. x86 is doing the same thing that (to my knowledge) all high-end processors do, yet no one tries to call out those chips as compiling to a different internal ISA. But you also don't see any chips trying to run with multiple ISA modes: the closest you get is 32-bit and 64-bit modes coexisting, or ARM's Thumb instruction set.

Re: RISC-V: They Should Have Known Better

#97

Is there a RISC-VI in the works where they try to learn from the RISC-V mistakes to make improvements?

Given the amount of learning that could have been done before RISC-V and wasn’t, I wouldn’t have such high hopes.

Considering just how many of the problems seem to come from RISC-V being a clean-sheet design, I suspect we would be better off not doing another.

What I am interested in is the idea doing an AArch64 style revamp of the ISA, were much of the non-encoding semantic stuff is kept, but the entire instruction encoding (plus all the CSRs, and other things) are reworked to be sane.

You might even do two reworkings in parallel, with one variable-width encoding optimised for microcontrollers, thumb-style; And the other being a fixed-width encoding optimised for wide out-of-order cores.

And at the same time, you make a bunch of extensions mandatory, and unify others into bigger chunks; Code compiled to one of these two encodings would know it had access to a much wider range of instructions.

The idea would be that any C code targeting RISC-V can be compiled to this encoding with close to zero changes, and that mechanical translation of exiting RISC-V binary code should be "possible", as none of the underlying semantics have changed. And the same would help any core wanting to natively support both (or all three) encodings, you would only need a front-end translator.

Re: RISC-V: They Should Have Known Better

#98
post #19
post #11

So … use RISC-V as the strawman, and create a community-based RISC-6 that doesn’t have these weaknesses? Better to get in now before it becomes too solidly entrenched.

You can't make a community-based ISA, it's not possible unless you have a community-based fab. He who makes the chips makes the rules.

I mean, a shuttle run is pretty cheap these days. If you have silicon, and customers, scaling past a shuttle run that worked is pretty low additional cost.

Re: RISC-V: They Should Have Known Better

#99

Earlier quoted context omitted.

> Of course not because that's impossible to prove. Why?

It's supposed to be impossible to prove a negative. But it might still happen some day. We just don't know.

"it's impossible to prove a negative" is a simplification. A negation is just the oppositive of an affirmation. If the affirmation is "there is an element E of an infinite set S that satisfies property P", the negation would be "there is no E in S that satisfy P", which would make proving by enumeration require checking every element of an infinite set, which is impossible. But other forms of proof might be possible.

The set of US patents, however, are not infinite and, IIRC, is also public. That said, IP laws are a mess.

Re: RISC-V: They Should Have Known Better

#100

Earlier quoted context omitted.

> Of course not because that's impossible to prove. Why?

It's supposed to be impossible to prove a negative. But it might still happen some day. We just don't know.

Well played
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