So … use RISC-V as the strawman, and create a community-based RISC-6 that doesn’t have these weaknesses? Better to get in now before it becomes too solidly entrenched.
RISC-V: They Should Have Known Better
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Re: RISC-V: They Should Have Known Better
#12RVA23 hardware is available (e.g. SpacemiT K3)
Re: RISC-V: They Should Have Known Better
#13I can definitely see his argument, although I still do believe RISC-V did a lot of things better than x86...
I really do hope that the arch is eventually able to fix this. Better that there be an open ISA than them all be closed IMO.
Re: RISC-V: They Should Have Known Better
#14> After being asked for the Nth time to explain, I decided to put it all down in one place so that I could simply link to it when asked next.
Bookmarked, because I've needed the same.
The worst part of all this is that they really should have known better by now. In 1980 you could make these kinds of mistakes, because this was pretty new territory. In 2020, doing this just makes you stupid. Or ignorant. Or both.
Re: RISC-V: They Should Have Known Better
#15It's clear that RISC-V started as an academic exercise (albeit from a group with esteemed credentials) and they had to bolt on these hacks to make it work in industry.
Sad.
Re: RISC-V: They Should Have Known Better
#16Why is he complaining about everything being optional in RISC-V? Isn't that the whole idea of RISC-V? The market can sort it out for themselves. RISC-V is already dominant in the MCU space despite its flaws, and many of them will be solved in due time.
Most MCUs are used for dead-simple solutions, like electric blankets and microwaves with segment displays or LEDs. Whether their interrupts are handled in 44 or 22 cycles doesn't really matter that much.
And RISC-V does have a link register, making returning much faster when the parameters for the interrupt can all fit in registers and no external memory access is needed, as is the case with most MCUs which put the stack in RAM. To fetch the return address an external memory access is always needed even if there are no parameters.
Re: RISC-V: They Should Have Known Better
#17I can definitely see his argument, although I still do believe RISC-V did a lot of things better than x86... I really do hope that the arch is eventually able to fix this. Better that there be an open ISA than them all be closed IMO.
Better than x86 is a low bar when ARMv8 exists.
Re: RISC-V: They Should Have Known Better
#18What happened to the Rivos accelerator cores?
Re: RISC-V: They Should Have Known Better
#19So … use RISC-V as the strawman, and create a community-based RISC-6 that doesn’t have these weaknesses? Better to get in now before it becomes too solidly entrenched.
You can't make a community-based ISA, it's not possible unless you have a community-based fab. He who makes the chips makes the rules.
Re: RISC-V: They Should Have Known Better
#20I think a lot of this criticism is completely true. However it's also overblown. I do think the ISA matters, but little mistakes like these definitely don't matter enough to preclude making M-series class chips. The reason it hasn't happened yet is simply time. It takes a really really long time to build up to that level of performance.
They've definitely gone overboard on the optionality stuff though. I don't think it matters too much for the actual CPU design but it makes verification and writing portable software a huge pain. Profiles definitely help but still...
Oh also I feel like you could probably come up with an equally compelling list about any other ISA. It's not like the fact that something has flaws means it's bad.