RISC-V: They Should Have Known Better • Hacker News Board

Re: RISC-V: They Should Have Known Better

#41

Post by hn_submit » Sat, Aug 15, 2026, 12:04 AM UTC

walrus01 wrote: post #26

hn_submit wrote: post #16

Why is he complaining about everything being optional in RISC-V? Isn't that the whole idea of RISC-V? The market can sort it out for themselves. RISC-V is already dominant in the MCU space despite its flaws, and many of them will be solved in due time. Most MCUs are used for dead-simple solutions, like electric blankets and microwaves with segment displays or LEDs. Whether their interrupts are handled in 44 or 22 cyc…

> The market can sort it out for themselves Because nobody will write software for 300 unique hardware variations of a platform that have inconsistent capabilities. Consistency is one of the reasons why x86-64 with extensions like like SSE, AVX2 etc is popular.

I believe the market will standardize on certain extensions for specific solutions. No one is going to make a mobile phone with only RV32I, for example.

Re: RISC-V: They Should Have Known Better

#42

Post by mappu » Sat, Aug 15, 2026, 12:06 AM UTC

tsukikage wrote: post #21

hn_submit wrote: post #16

Why is he complaining about everything being optional in RISC-V? Isn't that the whole idea of RISC-V? The market can sort it out for themselves. RISC-V is already dominant in the MCU space despite its flaws, and many of them will be solved in due time. Most MCUs are used for dead-simple solutions, like electric blankets and microwaves with segment displays or LEDs. Whether their interrupts are handled in 44 or 22 cyc…

He explains, at length: there is no sane way to determine what the hardware you are running on actually supports, and so there is no sane way to ship compiled code that is both compatible and performant. We already had the mystery meat CPU wars several decades ago. We know how to make sane ISAs now and should be past that.

I'm not sure this is a real problem - for embedded you know a priori - for arbitrary desktop/SBC machines, misa will be available in kernel mode and /proc/cpuinfo will be available in user mode.

Re: RISC-V: They Should Have Known Better

#43

Post by wren6991 » Sat, Aug 15, 2026, 12:10 AM UTC

RISC-V is... fine. It satisfies my two requirements for an ISA as a hobby CPU designer, which are:

1. Supported in mainline LLVM and GCC.

2. I can implement it without lawyers sending me a love letter.

Everything else, I can fix in post. There are enough good ideas spread across the extensions that I can assemble a reasonably put-together, curated embedded ISA with competitive performance and code density that admits a simple implementation.

I think Dmitry's points are largely on-target, though I have filed my usual statutory complaint that every rant that includes a bitfield diagram for the RISC-V J format should accompany it with a similar diagram for the Arm T32 BL encoding.

Re: RISC-V: They Should Have Known Better

#44

Post by hn_submit » Sat, Aug 15, 2026, 12:12 AM UTC

kjs3 wrote: post #33

hn_submit wrote: post #27

Earlier quoted context omitted.

You don't need to probe what hardware you're running on because you know being the manufacturer. The code is bespoke for your solution and nothing more. No foreign code is going to run on it. Different problems require different solutions. An electric blanket doesn't need a barrel shifter for multiplication or even floating point hardware. The ISA can change depending on what's needed to solve a particular problem, n…

I don't think I've read a more "doesn't actually know anything about how software is produced, but with absolute confidence knows everything about it" post in a very long time.

So you write software for a platform you know nothing about?

Re: RISC-V: They Should Have Known Better

#45

Post by kjs3 » Sat, Aug 15, 2026, 12:14 AM UTC

hn_submit wrote: post #44

kjs3 wrote: post #33

Earlier quoted context omitted.

I don't think I've read a more "doesn't actually know anything about how software is produced, but with absolute confidence knows everything about it" post in a very long time.

So you write software for a platform you know nothing about?

[flagged]

Re: RISC-V: They Should Have Known Better

#46

Post by gblargg » Sat, Aug 15, 2026, 12:14 AM UTC

Just noting, even if instructions were 100000000000000 bits long, reserving a single bit for 16-bit encoding would waste 50% of the instruction space.

Re: RISC-V: They Should Have Known Better

#47

Post by eek2121 » Sat, Aug 15, 2026, 12:15 AM UTC

Started reading, however I wanted to add this in: a lot of people expect RISC-V to do too many things, and nearly all of those things are "beat every other architecture out there in every way/shape/form, while also being open".

The reality? The fastest "available" RISC-V CPUs don't match the best chips in terms of speed, power consumption, or die area. "available" obviously means the chips that have been released to the public and can be independently benchmarked.

I do think that is okay, however I also think that those involved with RISC-V aren't helping much, and current attempts at standardizing seem to be just creating a bigger problem.

That being said, RISC-V does seem to perform well in specific niches.

Re: RISC-V: They Should Have Known Better

#48

Post by eek2121 » Sat, Aug 15, 2026, 12:24 AM UTC

IshKebab wrote: post #20

I think a lot of this criticism is completely true. However it's also overblown. I do think the ISA matters, but little mistakes like these definitely don't matter enough to preclude making M-series class chips. The reason it hasn't happened yet is simply time. It takes a really really long time to build up to that level of performance. They've definitely gone overboard on the optionality stuff though. I don't think…

ALL chip designs are an exercise of minmaxing these 3 variables:

1) power

2) performance

3) die area

SOME chip designs also care about a 4th:

4) die area.

NO design has the best of all...it is impossible since you have to trade 1 for another. The reason x86 has been dominate for so long is that is strikes a good balance across all areas, especially #4. A good balance is what you need for a good chip.

EDIT: oh and you can't beat the system I mentioned above. The laws of physics are the reason why.

Re: RISC-V: They Should Have Known Better

#49

Post by bjornnn » Sat, Aug 15, 2026, 12:24 AM UTC

the significance and allure of risc-v, the reason china is investing heavily in it right now, has little to do with the technical details of how it works under the hood, it's the fact that it is an open standard not encumbered by intellectual property law. even if it isn't technically the best general-purpose processor architecture, it sets an important precedent by proving that it is possible to develop an open public architecture that the world can use to build computing devices without being extorted by a multinational corporation charging licensing fees or a geopolitical superpower enacting tariffs and sanctions.

Re: RISC-V: They Should Have Known Better

#50

Post by phendrenad2 » Sat, Aug 15, 2026, 12:25 AM UTC

duskwuff wrote: post #37

NetMageSCW wrote: post #32

Earlier quoted context omitted.

Anther ISA like ARM? It seems pretty palatable to just about everyone not academic.

The ARM ISAs are not free to implement. ARM holds patents relevant to the ISA.

Until the patents expire, which many have already.