Permanent and global boycott of Samsung due to them shoving ads into smart refrigerators.
They’ll keep pushing till you push back.
Samsung demonstrates 3D stacked FETs with triple nanosheet channels at 42nm
31–40 of 49 posts
Re: Samsung demonstrates 3D stacked FETs with triple nanosheet channels at 42nm
#32Permanent and global boycott of Samsung due to them shoving ads into smart refrigerators. They’ll keep pushing till you push back.
Just don't buy smart refrigerators. They make other very good products.
Re: Samsung demonstrates 3D stacked FETs with triple nanosheet channels at 42nm
#33Permanent and global boycott of Samsung due to them shoving ads into smart refrigerators. They’ll keep pushing till you push back.
Good luck with that
Re: Samsung demonstrates 3D stacked FETs with triple nanosheet channels at 42nm
#34so whats the implication for average joes here ? have no idea what these technical terms mean....
Re: Samsung demonstrates 3D stacked FETs with triple nanosheet channels at 42nm
#35Permanent and global boycott of Samsung due to them shoving ads into smart refrigerators. They’ll keep pushing till you push back.
Basically every smart fridge they make has an equivalent (nearly identical) non-smart variant. You don't need a smart fridge, you don't need a screen on a fridge at all.
As an aside, my old Westinghouse fridge shows me ads. The ads arrive in my mailbox and then I put them on the fridge with a magnet. One of the ads on my fridge at the moment is for Dominos.
Re: Samsung demonstrates 3D stacked FETs with triple nanosheet channels at 42nm
#36Earlier quoted context omitted.
I'm not certain (never did hardware), but I thought the transistor switching cost was one of the bigger sources of energy loss, not internal conductor resistance between transistors?
The shorter connections could lead to faster rise times though, right? I.e. less capacitance or inductance interfering with getting the field gate charged up? And the main loss with switching transistors is in the intermediate switching states where it has less than its "full" resistance.
> The shorter connections could lead to faster rise times though, right?
Not if you replace that length with more capacitors stacked on top of each other.
Re: Samsung demonstrates 3D stacked FETs with triple nanosheet channels at 42nm
#37> By stacking multiple nanosheet channels, the effective channel width can be maintained even within a highly compact footprint. The fact that this level of precision can be achieved on 300mm wafers over many dozens of separate steps in separate devices is an insane achievement on its own.
A much greater achievement than training frontier models, or building any kind of software stack, if you ask me. Yet everybody seems to think the moat is with the AI companies or nvidia.
Now that it's been clear there's money to be made for a little while, inference engines will be commoditized the same way as bitcoin miners.
Re: Samsung demonstrates 3D stacked FETs with triple nanosheet channels at 42nm
#38so whats the implication for average joes here ? have no idea what these technical terms mean....
Computer chips go faster
Re: Samsung demonstrates 3D stacked FETs with triple nanosheet channels at 42nm
#39Earlier quoted context omitted.
Pure silicon melts at 1400 C You must be thinking of something else
I take your point, but an IC is not pure silicon
Indeed. For instance, dopants can diffuse and metals can intermix with silicon (silicide formation), both degrade device performance. Solder and packages melt before any of this happens.
Re: Samsung demonstrates 3D stacked FETs with triple nanosheet channels at 42nm
#40Earlier quoted context omitted.
Except hot spots quickly reach the melting point of silicon these days. That creates, let's say, a rather steep drop off in performance.
Pure silicon melts at 1400 C You must be thinking of something else
The melting of silicon was a common phenomenon already during the second breakdown of power transistors, e.g. in audio amplifiers or in TV sets, more than a half of century ago.
In semiconductors there is a positive feedback between temperature and the current that passes through them, so once a certain threshold is passed, the current and the temperature grow very quickly until the semiconductor is melted. This is opposite to the behavior of metals, where resistance grows with temperature, tending to limit the current that passes through the metal, when it overheats.
The currents through the transistors of SOTA logic gates are very small, but their volumes are also very small, so the power density is similar to that in high power transistors.
Thus thermal breakdown that leads to silicon melting is easily achievable. This is why any modern CPU has on-die temperature sensors, so that temperature is monitored and power dissipation is limited, to ensure that the threshold that triggers positive thermal feedback is never reached.