The fact that this level of precision can be achieved on 300mm wafers over many dozens of separate steps in separate devices is an insane achievement on its own.
Samsung demonstrates 3D stacked FETs with triple nanosheet channels at 42nm
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Re: Samsung demonstrates 3D stacked FETs with triple nanosheet channels at 42nm
#22> A city provides a useful analogy. When available land becomes scarce, urban planners initially reduce the spacing between buildings and use roads and open spaces more efficiently. Eventually, however, further horizontal expansion becomes impractical. At that point, the solution is to build upward. High-rise buildings create more usable space on the same piece of land by utilizing the vertical dimension. Really? som…
Retrofits are insanely expensive and often fraught with issues.
Re: Samsung demonstrates 3D stacked FETs with triple nanosheet channels at 42nm
#23Earlier quoted context omitted.
What you loose in heat you gain in speed caused by proximity. Perhaps this will allow for lower voltage and thus less heat.
Except hot spots quickly reach the melting point of silicon these days. That creates, let's say, a rather steep drop off in performance.
You must be thinking of something else
Re: Samsung demonstrates 3D stacked FETs with triple nanosheet channels at 42nm
#24Earlier quoted context omitted.
Except hot spots quickly reach the melting point of silicon these days. That creates, let's say, a rather steep drop off in performance.
Pure silicon melts at 1400 C You must be thinking of something else
Re: Samsung demonstrates 3D stacked FETs with triple nanosheet channels at 42nm
#25> By stacking multiple nanosheet channels, the effective channel width can be maintained even within a highly compact footprint. The fact that this level of precision can be achieved on 300mm wafers over many dozens of separate steps in separate devices is an insane achievement on its own.
Yet everybody seems to think the moat is with the AI companies or nvidia.
Re: Samsung demonstrates 3D stacked FETs with triple nanosheet channels at 42nm
#26Earlier quoted context omitted.
Except hot spots quickly reach the melting point of silicon these days. That creates, let's say, a rather steep drop off in performance.
Pure silicon melts at 1400 C You must be thinking of something else
Re: Samsung demonstrates 3D stacked FETs with triple nanosheet channels at 42nm
#27Earlier quoted context omitted.
Except hot spots quickly reach the melting point of silicon these days. That creates, let's say, a rather steep drop off in performance.
Pure silicon melts at 1400 C You must be thinking of something else
Re: Samsung demonstrates 3D stacked FETs with triple nanosheet channels at 42nm
#28This seems like it could accelerate the transition to sub-1nm nodes (previously projected to mid 2030s), maybe by the end of this decade.
Re: Samsung demonstrates 3D stacked FETs with triple nanosheet channels at 42nm
#29Earlier quoted context omitted.
Pure silicon melts at 1400 C You must be thinking of something else
Nope, thermodynamics is weird at small scales. Hot spots can absolutely reach 1400C if not designed not to. Sophie Wilson (initial architect of the ARM processor) has talked about how poorly designed silicon can reach point temperatures hotter than a nuclear reactor steady state.
Re: Samsung demonstrates 3D stacked FETs with triple nanosheet channels at 42nm
#30Earlier quoted context omitted.
Nope, thermodynamics is weird at small scales. Hot spots can absolutely reach 1400C if not designed not to. Sophie Wilson (initial architect of the ARM processor) has talked about how poorly designed silicon can reach point temperatures hotter than a nuclear reactor steady state.
That’s crazy. I thought maybe some of the other elements used in modern semiconductors might melt first. The wiring seems like a potential problem. But before that even the elements they use in the transistors themselves could be an issue.