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100x defect tolerance: How we solved the yield problem

cerebras.ai

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Re: 100x defect tolerance: How we solved the yield problem

#61

Post by donavanm »

abrookewood wrote: post #57

Looking at the H100 on the left, why is the chip yield (72) based on a circular layout/constraint? Why do they discard all of the other chips that fall outside the circle?

AFAIK all wafer ingots are cylinders, which means the wafers themselves are a circular cross section. So manufacturing is binpacking rectangles in to a circle. Plus different effects/defects in the chips based on the distance from the edge of the wafer.

So I believe its the opposite: why are they representing the larger square and implying lower yield off the wafer in space that doesnt practically exist?

Re: 100x defect tolerance: How we solved the yield problem

#62

Post by jjk166 »

ryao wrote: post #58

> Take the Nvidia H100 – a massive GPU weighing in at 814mm2. Traditionally this chip would be very difficult to yield economically. But since its cores (SMs) are fault tolerant, a manufacturing defect does not knock out the entire product. The chip physically has 144 SMs but the commercialized product only has 132 SMs active. This means the chip could suffer numerous defects across 12 SMs and still be sold as a flag…

Redundant cores lead to a fault tolerant chip.

Re: 100x defect tolerance: How we solved the yield problem

#63

Post by gpm »

daedrdev wrote: post #51
sroussey wrote: post #15

Earlier quoted context omitted.

I wonder if you could… just not cut the wafer at all??

That's the idea in the article. Just one big chip. But the reason why it's normally done is that there is a pretty high defect rate, so cutting if every wafer has 1-2 defects you still get (X-1.5) devices per wafer. In the article thy go into how they avoid this problem (I think its better fault tolerance, at a cost)

The article shows them using a single maximally sized square portion of a circular wafer.

I think the proposal you're responding to is "just use the whole circular wafer without cutting out a square".

Re: 100x defect tolerance: How we solved the yield problem

#64

Post by gpm »

yannyu wrote: post #23
olejorgenb wrote: post #21

Earlier quoted context omitted.

Yes, but my understanding is that the wafer is exposed in multiple steps, so there would still be less exposure steps? Probably insignificant compared to all the rest though. (Etching, moving the wafer, etc.) EDIT: to clarify - I mean the exposure of one single pattern/layer is done in multiple steps. ( https://en.wikipedia.org/wiki/Photolithography#Projection )

The number of exposure steps would be unrelated to the (surface area) size of die/device that you're making. In fact, in semiconductor manufacturing you're typically trying to maximize the number of devices per wafer because it costs the same to manufacture 1 device with 10 layers vs 100 devices with 10 layers on the same wafer. This goes so far as to have companies or business units share wafers for prototyping runs…

> This goes so far as to have companies or business units share wafers for prototyping runs so as to minimize cost per device

Can this be done in production? Is there a chance that the portion of the wafer cerebras.ai can't fit their giant square in is being used for production of some other companies chips?

Re: 100x defect tolerance: How we solved the yield problem

#65

Post by wmf »

ryao wrote: post #56
IshKebab wrote: post #7

TSMC also have a manufacturing process used by Tesla's Dojo where you can cut up the chips, throw away the defective ones, and then reassemble working ones into a sort of wafer scale device (5x5 chips for Dojo). Seems like a more logical design to me.

I had been under the impression that Nvidia had done something similar here, but they did not talk about deploying the space saving design and instead only talked about the server rack where all of the chips on the mega wafer normally are. https://www.sportskeeda.com/gaming-tech/what-nvlink72-nvidia...

That shield is just a prop that looks nothing like the real product. The NVL72 rack doesn't use any wafer-scale-like packaging.

Re: 100x defect tolerance: How we solved the yield problem

#67

Post by therealcamino »

abrookewood wrote: post #57

Looking at the H100 on the left, why is the chip yield (72) based on a circular layout/constraint? Why do they discard all of the other chips that fall outside the circle?

That's just the shape of the wafer. I don't know why the diagram continued the grid outside it.

Re: 100x defect tolerance: How we solved the yield problem

#68

Post by sitkack »

pulvinar wrote: post #20
olejorgenb wrote: post #6

Earlier quoted context omitted.

Is the wafer itself so expensive? I assume they don't pattern the unused area, so the process should be quicker?

There's also no reason they couldn't pattern that area with some other suitable commodity chips. Like how sawmills and butchers put all cuts to use.

Often those areas are used for test chips and structures for the next version. They are effectively free, so you can use them to test out ideas.

Re: 100x defect tolerance: How we solved the yield problem

#69

Post by ericye16 »

kristjansson wrote: post #53
lostlogin wrote: post #31

Earlier quoted context omitted.

If rack mounted, you are ending up with something like a reverse power station. So why not use it as an energy source? Spin a turbine.

If you let the chip actual boil enough water to run a turbine you're going to have a hard time keeping the magic smoke inside. Much better to run at reasonable temps and try to recover energy from the waste heat.

What if you chose a refrigerant with a lower boiling point?

Re: 100x defect tolerance: How we solved the yield problem

#70

Post by renhanxue »

lostlogin wrote: post #31
NickHoff wrote: post #27

Neat. What about power density? An H100 has a TDP of 700 watts (for the SXM5 version). With a die size of 814 mm^2 that's 0.86 W/mm^2. If the cerebras chip has the same power density, that means a cerebras TDP of 37.8 kW. That's a lot. Let's say you cover the whole die area of the chip with water 1 cm deep. How long would it take to boil the water starting from room temperature (20 degrees C)? amount of water = (die…

If rack mounted, you are ending up with something like a reverse power station. So why not use it as an energy source? Spin a turbine.

There's a bunch of places in Europe that use waste heat from datacenters in district heating systems. Same thing with waste heat from various industrial processes. It's relatively common practice.
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