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100x defect tolerance: How we solved the yield problem

cerebras.ai

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Re: 100x defect tolerance: How we solved the yield problem

#51

Post by daedrdev »

sroussey wrote: post #15
guyzero wrote: post #10

Earlier quoted context omitted.

I've never cut a wafer, but I assume cutting is hard and single straight lines are the easiest.

I wonder if you could… just not cut the wafer at all??

That's the idea in the article. Just one big chip. But the reason why it's normally done is that there is a pretty high defect rate, so cutting if every wafer has 1-2 defects you still get (X-1.5) devices per wafer. In the article thy go into how they avoid this problem (I think its better fault tolerance, at a cost)

Re: 100x defect tolerance: How we solved the yield problem

#52

Post by addaon »

olejorgenb wrote: post #6
ajb wrote: post #4

So they massively reduce the area lost to defects per wafer, from 361 to 2.2 square mm. But from the figures in this blog, this is massively outweighed by the fact that they only get 46222 sq mm useable area out of the wafer, as opposed to 56247 that the H100 gets - because they are using a single square die instead of filling the circular wafer with smaller square dies, they lose 10,025 sq mm! Not sure how that's a…

Is the wafer itself so expensive? I assume they don't pattern the unused area, so the process should be quicker?

> I assume they don't pattern the unused area

I’m out of date on this stuff, so it’s possible things have changed, but I wouldn’t make that assumption. It is (used to be?) standard to pattern the entire wafer, with partially-off-the-wafer dice around the edges of the circle. The reason for this is that etching behavior depends heavily on the surrounding area — the amount of silicon or copper whatever etched in your neighborhood affects the speed of etching for you, which effects line width, and (for a single mask used for the whole wafer) thus either means you need to have more margin on your parameters (equivalent to running on an old process) or have a higher defect right near the edge of the die (which you do anyway, since you can only take “similar neighborhood” so far). This goes as far as, for hyper-optimized things like SRAM arrays, leaving an unused row and column at each border of the array.

Re: 100x defect tolerance: How we solved the yield problem

#53

Post by kristjansson »

lostlogin wrote: post #31
NickHoff wrote: post #27

Neat. What about power density? An H100 has a TDP of 700 watts (for the SXM5 version). With a die size of 814 mm^2 that's 0.86 W/mm^2. If the cerebras chip has the same power density, that means a cerebras TDP of 37.8 kW. That's a lot. Let's say you cover the whole die area of the chip with water 1 cm deep. How long would it take to boil the water starting from room temperature (20 degrees C)? amount of water = (die…

If rack mounted, you are ending up with something like a reverse power station. So why not use it as an energy source? Spin a turbine.

If you let the chip actual boil enough water to run a turbine you're going to have a hard time keeping the magic smoke inside. Much better to run at reasonable temps and try to recover energy from the waste heat.

Re: 100x defect tolerance: How we solved the yield problem

#54

Post by ryao »

sroussey wrote: post #15
guyzero wrote: post #10

Earlier quoted context omitted.

I've never cut a wafer, but I assume cutting is hard and single straight lines are the easiest.

I wonder if you could… just not cut the wafer at all??

I suspect this would cause alignment issues since you could literally rotate it into the wrong position when doing soldering. That said, perhaps they could get away with cutting less and using more.

Re: 100x defect tolerance: How we solved the yield problem

#56

Post by ryao »

IshKebab wrote: post #7

TSMC also have a manufacturing process used by Tesla's Dojo where you can cut up the chips, throw away the defective ones, and then reassemble working ones into a sort of wafer scale device (5x5 chips for Dojo). Seems like a more logical design to me.

I had been under the impression that Nvidia had done something similar here, but they did not talk about deploying the space saving design and instead only talked about the server rack where all of the chips on the mega wafer normally are.

https://www.sportskeeda.com/gaming-tech/what-nvlink72-nvidia...

Re: 100x defect tolerance: How we solved the yield problem

#58

Post by ryao »

> Take the Nvidia H100 – a massive GPU weighing in at 814mm2. Traditionally this chip would be very difficult to yield economically. But since its cores (SMs) are fault tolerant, a manufacturing defect does not knock out the entire product. The chip physically has 144 SMs but the commercialized product only has 132 SMs active. This means the chip could suffer numerous defects across 12 SMs and still be sold as a flagship part.

Fault tolerance seems to be the wrong term to use here. If I wrote this, I would have written redundant.

Re: 100x defect tolerance: How we solved the yield problem

#59

Post by flumpcakes »

abrookewood wrote: post #57

Looking at the H100 on the left, why is the chip yield (72) based on a circular layout/constraint? Why do they discard all of the other chips that fall outside the circle?

Because the circle is the physical silicon. Any chips that fall outside the circle are only part of a full chip. They will be physically missing half the chip.
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