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100x defect tolerance: How we solved the yield problem

cerebras.ai

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Re: 100x defect tolerance: How we solved the yield problem

#31

Post by lostlogin »

NickHoff wrote: post #27

Neat. What about power density? An H100 has a TDP of 700 watts (for the SXM5 version). With a die size of 814 mm^2 that's 0.86 W/mm^2. If the cerebras chip has the same power density, that means a cerebras TDP of 37.8 kW. That's a lot. Let's say you cover the whole die area of the chip with water 1 cm deep. How long would it take to boil the water starting from room temperature (20 degrees C)? amount of water = (die…

If rack mounted, you are ending up with something like a reverse power station.

So why not use it as an energy source? Spin a turbine.

Re: 100x defect tolerance: How we solved the yield problem

#32

Post by kristjansson »

olejorgenb wrote: post #6
ajb wrote: post #4

So they massively reduce the area lost to defects per wafer, from 361 to 2.2 square mm. But from the figures in this blog, this is massively outweighed by the fact that they only get 46222 sq mm useable area out of the wafer, as opposed to 56247 that the H100 gets - because they are using a single square die instead of filling the circular wafer with smaller square dies, they lose 10,025 sq mm! Not sure how that's a…

Is the wafer itself so expensive? I assume they don't pattern the unused area, so the process should be quicker?

AIUI Wafer marginal cost is lower than you'd expect. I had $50k in my head, quick google indicates[1] maybe [1] https://www.tomshardware.com/tech-industry/tsmcs-wafer-prici...

Re: 100x defect tolerance: How we solved the yield problem

#33

Post by buildbot »

NickHoff wrote: post #27

Neat. What about power density? An H100 has a TDP of 700 watts (for the SXM5 version). With a die size of 814 mm^2 that's 0.86 W/mm^2. If the cerebras chip has the same power density, that means a cerebras TDP of 37.8 kW. That's a lot. Let's say you cover the whole die area of the chip with water 1 cm deep. How long would it take to boil the water starting from room temperature (20 degrees C)? amount of water = (die…

A Very Fancy cooling engine: https://www.eetimes.com/powering-and-cooling-a-wafer-scale-d...

Re: 100x defect tolerance: How we solved the yield problem

#34

Post by sebzim4500 »

lostlogin wrote: post #31
NickHoff wrote: post #27

Neat. What about power density? An H100 has a TDP of 700 watts (for the SXM5 version). With a die size of 814 mm^2 that's 0.86 W/mm^2. If the cerebras chip has the same power density, that means a cerebras TDP of 37.8 kW. That's a lot. Let's say you cover the whole die area of the chip with water 1 cm deep. How long would it take to boil the water starting from room temperature (20 degrees C)? amount of water = (die…

If rack mounted, you are ending up with something like a reverse power station. So why not use it as an energy source? Spin a turbine.

If my very stale physics is accurate then even with perfect thermodynamic efficiency you would only recover about a third of the energy that you put into the chips.

Re: 100x defect tolerance: How we solved the yield problem

#35

Post by [deleted] »

olejorgenb wrote: post #6
ajb wrote: post #4

So they massively reduce the area lost to defects per wafer, from 361 to 2.2 square mm. But from the figures in this blog, this is massively outweighed by the fact that they only get 46222 sq mm useable area out of the wafer, as opposed to 56247 that the H100 gets - because they are using a single square die instead of filling the circular wafer with smaller square dies, they lose 10,025 sq mm! Not sure how that's a…

Is the wafer itself so expensive? I assume they don't pattern the unused area, so the process should be quicker?

[deleted]

Re: 100x defect tolerance: How we solved the yield problem

#36

Post by dylan604 »

sebzim4500 wrote: post #34
lostlogin wrote: post #31

Earlier quoted context omitted.

If rack mounted, you are ending up with something like a reverse power station. So why not use it as an energy source? Spin a turbine.

If my very stale physics is accurate then even with perfect thermodynamic efficiency you would only recover about a third of the energy that you put into the chips.

1/3 > 0, so even if you don't get a $0 energy bill I'd venture that any company that could get 1/3 of energy bill would be happy

Re: 100x defect tolerance: How we solved the yield problem

#37

Post by dylan604 »

bigmattystyles wrote: post #30

When I was a kid, I used to get intel keychains with a die in acrylic - good job to whoever thought of that to sell the fully defective chips.

wow, fancy with the acrylic. lots of places just place a chip (I'm more familiar with RAM sticks) on a keychain and call it a day.

Re: 100x defect tolerance: How we solved the yield problem

#38

Post by jwan584 »

NickHoff wrote: post #27

Neat. What about power density? An H100 has a TDP of 700 watts (for the SXM5 version). With a die size of 814 mm^2 that's 0.86 W/mm^2. If the cerebras chip has the same power density, that means a cerebras TDP of 37.8 kW. That's a lot. Let's say you cover the whole die area of the chip with water 1 cm deep. How long would it take to boil the water starting from room temperature (20 degrees C)? amount of water = (die…

A good talk on how Cerebras does power & cooling (8min) https://www.youtube.com/watch?v=wSptSOcO6Vw&ab_channel=Appli...

Re: 100x defect tolerance: How we solved the yield problem

#40

Post by Neywiny »

Understanding that there's inherent bias by them being competitors of the other companies, but still this article seems to make some stretches. If you told me you had an 8% core defect rate reduced 100x, I'd assume you got to close to 99% enablement. The table at the end shows... Otherwise.

They also keep flipping between cores, SMs, dies, and maybe other block sizes. At the end of the day I'm not very impressed. They seemingly have marginally better yields despite all that effort.

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