I got almost all of my wishes granted with RP2350

Post by moffkalast » Thu, Aug 08, 2024, 4:29 PM UTC

coder543 wrote: post #47

swetland wrote: post #44

Earlier quoted context omitted.

They actually let you choose one Cortex-M33 and one RISC-V RV32 as an option (probably not going to be a very common use case) and support atomic instructions from both cores.

All of the public mentions of this feature that I've seen indicated it is an either/or scenario, except the datasheet confirms what you're saying: > The ARCHSEL register has one bit for each processor socket, so it is possible to request mixed combinations of Arm and RISC-V processors: either Arm core 0 and RISC-V core 1, or RISC-V core 0 and Arm core 1. Practical applications for this are limited, since this require…

Post by ta988 » Thu, Aug 08, 2024, 4:37 PM UTC

HeyLaughingBoy wrote: post #41

dave78 wrote: post #7

Earlier quoted context omitted.

Pico 2, using the 2350, seems to be announced: https://www.raspberrypi.com/products/raspberry-pi-pico-2/

Make one in an Arduino Uno form factor and double the price and they'd make a killing :-) I try to dissuade n00bs from starting their arduino journey with the ancient AVR-based devices, but a lot of the peripherals expect to plug into an Uno.

Post by geerlingguy » Thu, Aug 08, 2024, 4:38 PM UTC

coder543 wrote: post #47

swetland wrote: post #44

Earlier quoted context omitted.

They actually let you choose one Cortex-M33 and one RISC-V RV32 as an option (probably not going to be a very common use case) and support atomic instructions from both cores.

All of the public mentions of this feature that I've seen indicated it is an either/or scenario, except the datasheet confirms what you're saying: > The ARCHSEL register has one bit for each processor socket, so it is possible to request mixed combinations of Arm and RISC-V processors: either Arm core 0 and RISC-V core 1, or RISC-V core 0 and Arm core 1. Practical applications for this are limited, since this require…

Post by geerlingguy » Thu, Aug 08, 2024, 4:40 PM UTC

fouronnes3 wrote: post #48

Curious about the low-power and sleep mode improvements!

Post by zer00eyz » Thu, Aug 08, 2024, 4:44 PM UTC

bri3d wrote: post #46

synergy20 wrote: post #19

You can pick either ARM cores or RISC-V cores on the same die? Never saw design like this before. Will this impact price and power consumption? "The Hazard3 cores are optional: Users can at boot time select a pair of included Arm Cortex-M33 cores to run, or the pair of Hazard3 cores. Both options run at 150 MHz. The more bold could try running one RV and one Arm core together rather than two RV or two Arm. Hazard3 is…

This "switchable cores" thing has been appearing in some products for a few years now, for example Sipeed SG2002 (LicheeRV). The area occupied by the actual instruction core is usually pretty small compared to peripherals and internal memories.