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I got almost all of my wishes granted with RP2350

dmitry.gr

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Re: I got almost all of my wishes granted with RP2350

#41
post #7
post #2

Can’t find an official announcement or datasheet yet, but according to this post: * 2x Cortex-M33F * improved DMA * more and improved PIO * external PSRAM support * variants with internal flash (2MB) and 80 pins (!) * 512KiB ram (double) * some RISC-V cores? Low power maybe? Looks like a significant jump over the RP2040!

Pico 2, using the 2350, seems to be announced: https://www.raspberrypi.com/products/raspberry-pi-pico-2/

Make one in an Arduino Uno form factor and double the price and they'd make a killing :-)

I try to dissuade n00bs from starting their arduino journey with the ancient AVR-based devices, but a lot of the peripherals expect to plug into an Uno.

Re: I got almost all of my wishes granted with RP2350

#42
post #2

Can’t find an official announcement or datasheet yet, but according to this post: * 2x Cortex-M33F * improved DMA * more and improved PIO * external PSRAM support * variants with internal flash (2MB) and 80 pins (!) * 512KiB ram (double) * some RISC-V cores? Low power maybe? Looks like a significant jump over the RP2040!

I'm hoping that its got much better power management. That would be really cool for me.

Re: I got almost all of my wishes granted with RP2350

#43

Some specs here: https://www.digikey.ca/en/product-highlight/r/raspberry-pi/r... Based on the RP2350, designed by Raspberry Pi in the United Kingdom Dual Arm M33s at 150 MHz with FPU 520 KiB of SRAM Robust security features (signed boot, OTP, SHA-256, TRNG, glitch detectors and Arm TrustZone for Cortex®-M) Optional, dual RISC-V Hazard3 CPUs at 150 MHz Low-power operation PIO v2 with 3 × programmable I/O co-processors…

Wow, can't wait. Love the 5V GPIO and security features.

5V GPIO is a huge deal for me - this immediately opens up a huge range of integrations without having to worry about line level conversion.

I can’t wait to use this!

Re: I got almost all of my wishes granted with RP2350

#44

Can someone explain the benefit of having essentially 4 cores (2 ARM + 2 RISC-V) on the chip but only having 2 able to run simultaneously? Does this take significantly less die space than having all 4 available at all times?

Coordinating access to the memory bus and peripherals is probably not easy to do when the cores weren’t ever designed to work together. Doing so could require a power/performance penalty at all times, even though most users are unlikely to want to deal with two completely different architectures across four cores on one microcontroller. Having both architectures available is a cool touch. I believe I criticized the o…

They actually let you choose one Cortex-M33 and one RISC-V RV32 as an option (probably not going to be a very common use case) and support atomic instructions from both cores.

Re: I got almost all of my wishes granted with RP2350

#46

You can pick either ARM cores or RISC-V cores on the same die? Never saw design like this before. Will this impact price and power consumption? "The Hazard3 cores are optional: Users can at boot time select a pair of included Arm Cortex-M33 cores to run, or the pair of Hazard3 cores. Both options run at 150 MHz. The more bold could try running one RV and one Arm core together rather than two RV or two Arm. Hazard3 is…

This "switchable cores" thing has been appearing in some products for a few years now, for example Sipeed SG2002 (LicheeRV). The area occupied by the actual instruction core is usually pretty small compared to peripherals and internal memories.

Re: I got almost all of my wishes granted with RP2350

#47

Earlier quoted context omitted.

Coordinating access to the memory bus and peripherals is probably not easy to do when the cores weren’t ever designed to work together. Doing so could require a power/performance penalty at all times, even though most users are unlikely to want to deal with two completely different architectures across four cores on one microcontroller. Having both architectures available is a cool touch. I believe I criticized the o…

They actually let you choose one Cortex-M33 and one RISC-V RV32 as an option (probably not going to be a very common use case) and support atomic instructions from both cores.

All of the public mentions of this feature that I've seen indicated it is an either/or scenario, except the datasheet confirms what you're saying:

> The ARCHSEL register has one bit for each processor socket, so it is possible to request mixed combinations of Arm and RISC-V processors: either Arm core 0 and RISC-V core 1, or RISC-V core 0 and Arm core 1. Practical applications for this are limited, since this requires two separate program images.

That is fascinating... so, likely what dmitrygr said about the size of the crossbar sounds right to me: https://news.ycombinator.com/item?id=41192580

Re: I got almost all of my wishes granted with RP2350

#49

Not off topic but a bit tangentially... How difficult would be emulating an old SRAM chip with an RP2040 or an RP2350? It's an early 80s (or older) 2048 word, 200ns access time CMOS SRAM that is used to save presets on an old Casio synth. It's not a continuous memory read, it just reads when loading the preset to memory. I feel like PIO would be perfect for that.

I did that, not just SRAM but also ROM, to fool a MC68EZ328 successfully. It works well. PIO + DMA does it well. Specifically i replaced rom & ram in an old Palm Pilot with an RP2040: https://photos.app.goo.gl/KabVe5CrfckqnFEt7 https://photos.app.goo.gl/LGAkp6HoYAJc3Uft7 Edit: I did not yet update the rePalm article but much about that is in the Palm discord. https://discord.gg/qs8wQ4Bf see #repalm-project channel

Ooooh, that looks cool and the PCB seems simple (at least from this side). Congrats!

Do you have anything published?

Re: I got almost all of my wishes granted with RP2350

#50

Some specs here: https://www.digikey.ca/en/product-highlight/r/raspberry-pi/r... Based on the RP2350, designed by Raspberry Pi in the United Kingdom Dual Arm M33s at 150 MHz with FPU 520 KiB of SRAM Robust security features (signed boot, OTP, SHA-256, TRNG, glitch detectors and Arm TrustZone for Cortex®-M) Optional, dual RISC-V Hazard3 CPUs at 150 MHz Low-power operation PIO v2 with 3 × programmable I/O co-processors…

> Low-power operation

Low power suspend? In a Pi Foundation product? Impossible.

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