11–20 of 356 posts
Can’t find an official announcement or datasheet yet, but according to this post: * 2x Cortex-M33F * improved DMA * more and improved PIO * external PSRAM support * variants with internal flash (2MB) and 80 pins (!) * 512KiB ram (double) * some RISC-V cores? Low power maybe? Looks like a significant jump over the RP2040!
Can’t find an official announcement or datasheet yet, but according to this post: * 2x Cortex-M33F * improved DMA * more and improved PIO * external PSRAM support * variants with internal flash (2MB) and 80 pins (!) * 512KiB ram (double) * some RISC-V cores? Low power maybe? Looks like a significant jump over the RP2040!
Pico 2, using the 2350, seems to be announced: https://www.raspberrypi.com/products/raspberry-pi-pico-2/
Some specs here: https://www.digikey.ca/en/product-highlight/r/raspberry-pi/r... Based on the RP2350, designed by Raspberry Pi in the United Kingdom Dual Arm M33s at 150 MHz with FPU 520 KiB of SRAM Robust security features (signed boot, OTP, SHA-256, TRNG, glitch detectors and Arm TrustZone for Cortex®-M) Optional, dual RISC-V Hazard3 CPUs at 150 MHz Low-power operation PIO v2 with 3 × programmable I/O co-processors…
Some specs here: https://www.digikey.ca/en/product-highlight/r/raspberry-pi/r... Based on the RP2350, designed by Raspberry Pi in the United Kingdom Dual Arm M33s at 150 MHz with FPU 520 KiB of SRAM Robust security features (signed boot, OTP, SHA-256, TRNG, glitch detectors and Arm TrustZone for Cortex®-M) Optional, dual RISC-V Hazard3 CPUs at 150 MHz Low-power operation PIO v2 with 3 × programmable I/O co-processors…
Is there an exhaustive list of stm32h7 errata? Has anyone compiled a defect list?
Speak of the devil: https://news.ycombinator.com/item?id=41156743 Very nice that the "3" turned out to mean the modern M33 core rather than the much older M3 core. It has a real FPU!
"The Hazard3 cores are optional: Users can at boot time select a pair of included Arm Cortex-M33 cores to run, or the pair of Hazard3 cores. Both options run at 150 MHz. The more bold could try running one RV and one Arm core together rather than two RV or two Arm.
Hazard3 is an open source design, and all the materials for it are here. It's a lightweight three-stage in-order RV32IMACZb* machine, which means it supports the base 32-bit RISC-V ISA with support for multiplication and division in hardware, atomic instructions, bit manipulation, and more."
4 variants? "A" and "B" variants in QFN60 and QFN80, "2350" and "2354" variants with and without 2MB Flash. CPU can be switched between dual RISC-V @ 150MHz or dual Cortex-M33 @ 300MHz by software or in one-time programming memory(=permanently).
Datasheet, core switching details, most of docs are 404 as of now; I guess they didn't have embargo date actually written in `crontab`.
e: and datasheet is up!