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TSMC unveils 1.6nm process technology with backside power delivery

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Re: TSMC unveils 1.6nm process technology with backside power delivery

#201

Post by fennecbutt »

hinkley wrote: post #117
s3p wrote: post #107

Earlier quoted context omitted.

OP isn't wrong. Once the switch was made from 2D to 3D gates, transistor numbering became "this is the performance you would expect if you COULD shrink a gate to x nm", and while it's inaccurate it lets people understand how differentiated a new generation is from the previous ones. It also lets them stay consistent with understanding the progression of chips over time as in most of the history of silicon the generat…

We should have switched to gates per mm² long ago. IMO that covers the 3D problem fine. Doesn’t cover variance in feature size by task though. If the gates for a multiplier or cache need more space per gate than a logical OR then the marketing guys still get a little victory over truth. We could just divide total gates by surface area for the chip, but that would confuse the process efficiency with the implementation…

I'd say mm3 really, means it works going into the future when we can hopefully make something like a 10mm3 chunk of silicon. Gimme that computronium!

Re: TSMC unveils 1.6nm process technology with backside power delivery

#202

Post by hinkley »

fennecbutt wrote: post #201
hinkley wrote: post #117

Earlier quoted context omitted.

We should have switched to gates per mm² long ago. IMO that covers the 3D problem fine. Doesn’t cover variance in feature size by task though. If the gates for a multiplier or cache need more space per gate than a logical OR then the marketing guys still get a little victory over truth. We could just divide total gates by surface area for the chip, but that would confuse the process efficiency with the implementation…

I'd say mm3 really, means it works going into the future when we can hopefully make something like a 10mm3 chunk of silicon. Gimme that computronium!

We know that height is a thermal dissipation issue. If someone can figure out how to make taller chips then good for them. Any time a chip goes vertical you also reduce speed of light delay between units, so it still has effects we desire and want to push.

mm² is perfectly adequate for what we are after.

Re: TSMC unveils 1.6nm process technology with backside power delivery

#203

Post by ric2b »

satiric wrote: post #171
Detrytus wrote: post #146

Earlier quoted context omitted.

Gallons per hundred miles would be more useful. I guess it's a matter of approach. Europeans are traveling familiar, constant distances and worry about fuel cost. Americans just fill up their tank and worry how far they can go :)

If I buy 2 gallons of gas, and my car gets 30 mpg, then I can go 60 miles. Doesn't seem that hard to me. Need the other way around? I need to go 100 miles. At 30 miles per gallon, that's a little over 3 gallons. This is simple mental math.

From: https://www.popularmechanics.com/cars/a12367/4324986/

"Quick, which is better: Replacing an 18-mpg car with a 28-mpg one, or going from a 34-mpg car to one that returns 50 mpg? Researchers at Duke University say that drivers find it easier to select the right answer when efficiency is expressed as gallons per 100 miles (g/100m).

So 18 mpg (or 5.5 g/100m) versus 28 mpg (3.6 g/100m)--an increase of 10 mpg--represents a 52 percent reduction in consumption.

If you trade in a car rated at 34 mpg for one rated at 50 mpg, its a 16-mpg improvement, so we ought to see those gas card bills plummeting, right? Actually, after a minute's worth of math, you'll get 2.9g/100m in the 34-mpg car and 2g/100m in the 50-mpg car--only half as big a gain as the original scenario. "

Re: TSMC unveils 1.6nm process technology with backside power delivery

#204

Post by ric2b »

bee_rider wrote: post #167
black_puppydog wrote: post #131

Earlier quoted context omitted.

Stupid beginner question: is MTr/mm² really the right thing to be looking at? Shouldn't it be more like mm²/MTr ? This feels kind of like these weird "miles per gallon" units, when "gallons per mile" is much more useful...

What’s the argument for either? They are, of course, equivalent… might as well pick the one where bigger=better.

This page has the arguments in favor or fuel consumed per distance travelled: https://www.popularmechanics.com/cars/a12367/4324986/

Re: TSMC unveils 1.6nm process technology with backside power delivery

#205

Post by bee_rider »

exe34 wrote: post #188
bee_rider wrote: post #168

Earlier quoted context omitted.

I don’t think they drop the dimensions, just the constants.

It's equivalent to the 1.6nm != 1.6 nm though.

I mean, I get that this is a joke so I’m not going to over-analyze it, but using the fundamental physics constants as units is a totally reasonable thing to do, and nothing like using nm as a unit of… area? Density? Marketing term? It is a mess whatever it is.

Re: TSMC unveils 1.6nm process technology with backside power delivery

#206

Post by kvemkon »

Sysreq2 wrote: post #95
Workaccount2 wrote: post #63

Earlier quoted context omitted.

Intel has a 1.4nm process in the pipeline for ~2027. They just took delivery on their first high NA EUV machine in order to start working on it. Their gamble however is that they need to figure out DSA, a long storied technology that uses self-forming polymers to allow less light to sharply etch smaller features. If they figure out DSA, they will likely be ahead of TSMC. If not, it will just be more very expensive la…

The nomenclature for microchip manufacturing left reality a couple generations ago. Intel’s 14A process is not a true 14A half-pitch. It’s kind of like how they started naming CPUs off “performance equivalents” instead of using raw clock speed. And this isn’t just Intel. TSMC, Samsung, everyone is doing half-pitch equivalent naming now a days. This is the industry roadmap from 2022: https://irds.ieee.org/images/files…

> Intel’s 14A process is not a true 14A half-pitch. It’s kind of like how they started naming CPUs off “performance equivalents” instead of using raw clock speed.

Earlier it was AMD. The most prominent era since their Athlon XP CPUs turned out to be noticeably more performant per GHz than Intel in 2001.

Re: TSMC unveils 1.6nm process technology with backside power delivery

#207

Post by lostlogin »

thsksbd wrote: post #198
Tagbert wrote: post #73

Earlier quoted context omitted.

it also seems to be a roughly proportional change in density so why would it be unhelpful? Just because you can't point to a specific feature and say that is 1.6nm, doesn't make the label meaningless as so many try to assert. It is a label that represents a process that results in a specific transistor density. What label would you prefer?

... transistor density?

Correct. Or something else that allowed comparison between fabs without me having to read a ton of explanations.

Re: TSMC unveils 1.6nm process technology with backside power delivery

#208

Post by blagie »

brennanpeterson wrote: post #175
blagie wrote: post #37

Earlier quoted context omitted.

This isn't quite right. Big wires (ideally entire planes) deliver power. Small wires deliver signal. Half and half isn't the right split, and you don't want to make power wires smaller. The very different requirements of the two is where a lot of the gains come in.

True! I went a little far in the name of 'eli5'. I think it roughly holds that you gain about a factor of 1.5 in routing density by removing the power distribution, so you can relax some critical patterning. But I havent looked closely in a long time.

Oft-missed pedagogical point for working with five-year-olds:

Precision is important. You'll notice every comment I made was as simple as I can make it, but /technically correct/. I did not oversimplify to where I changed facts.

* It's okay if five-year-olds don't fully understand something. That builds exposure, and leaves a placeholder for future information and curiosity.

* On the other hand, if you build out an array of misconceptions, those become very expensive to address later.

To a large extent, the younger the child, the more comfortable they will be with being told things they don't understand. A baby doesn't care if you're reading them a book on trucks or a book on homeomorphic transformations; they're picking out the phonemes. A toddler will trust you as an adult, and won't understand 90% of the stuff they hear anyways. A five-year-old, you can still say a lot they won't understand and they'll be not just okay but happy. By maybe seven, lack-of-understanding will become frustrating, and in most cases, by eleven, it's gone.

I could write a long essay on this stuff, and why it's so important to maintain that ability to be confused and half-understand, but I very intentionally leave placeholders when working with five-year-olds.

Re: TSMC unveils 1.6nm process technology with backside power delivery

#209

Post by SilverBirch »

onepointsixC wrote: post #148
SilverBirch wrote: post #111

Earlier quoted context omitted.

There are definitely going to be people taking a bet on the Intel foundry, but Intel has tried this before and it has worked badly.

Sounds like an easy short for you then.

I worked for Intel at a point where it was clear they were going to miss every important technical milestone you could name. The stock stayed high through every bad piece of news and was only when Gelsinger bit the bullet and told the truth that the stock actually tumbled, and it still didn't tumble back to below the point they were when it was obvious they were in trouble. In fact it reached really good high points long after it was obvious they were in trouble.

Shorting is for only the most incontrovertible frauds as far as I'm concerned.

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