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TSMC unveils 1.6nm process technology with backside power delivery

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Re: TSMC unveils 1.6nm process technology with backside power delivery

#141

Post by choilive »

merb wrote: post #132
7thpower wrote: post #87

Earlier quoted context omitted.

Yes, generally one of the trends has been movement toward specialized coprocessors/accelerators. This was happening before the recent AI push and has picked up steam. If you think of an SOC, the chip in your phone, more and more of the real estate is being dedicated to specialized compute (AI accelerators, GPUs, etc. vs general purpose compute (CPU). At the enterprise scale, one of the big arguments NVIDIA has been m…

JavaScript accelerator would probably half the power consumption of the world. The problem is just, that as soon as it would have widespread usage it would probably already be too old.

I believe ARM has some instructions that is JavaScript specific so we're kinda in that direction already.

Re: TSMC unveils 1.6nm process technology with backside power delivery

#142

Post by simpsond »

black_puppydog wrote: post #131
futureshock wrote: post #59

Comments about the marketing driven nm measurements aside, this still looks like another solid advance for TSMC. They are already significantly ahead of Samsung and Intel on transistor density. TSMC is at 197 MTr/mm2 wile Samsung is at 150 MTr/mm2 and Intel is at 123 MTr/mm2. This 1.6nm process will put them around 230 MTr/mm2 by 2026. When viewed by this metric, Intel is really falling behind.

Stupid beginner question: is MTr/mm² really the right thing to be looking at? Shouldn't it be more like mm²/MTr ? This feels kind of like these weird "miles per gallon" units, when "gallons per mile" is much more useful...

200 million transistors per square millimeter.

Gallons per mile only makes sense when you are talking about dragsters.

Re: TSMC unveils 1.6nm process technology with backside power delivery

#143

Post by ahartmetz »

Rinzler89 wrote: post #85
saganus wrote: post #69

Earlier quoted context omitted.

Do you know the name of the company that produces the EUV machine? is it ASML? It is my understanding that only ASML had cracked the EUV litography, but if there's another company out there, that would be an interesting development to watch.

>It is my understanding that only ASML had cracked the EUV litography Ackshually , EUV was cracked by Sandia Labs research in the US, with EUV light sources built by Cymer in the US. ASML was the only one allowed to license the tech and integrate it into their steppers after they bough Cymer in 2013. Hence why US has veto rights to whom Dutch based ASML can sell their EUV steppers to, as in not to China, despite ow m…

>EUV was cracked

More like it was started. There were a ton of gnarly problems left that took over ten years and billions of € to solve.

Producing a few flashes of EUV and getting a few photons on the target is relatively easy. Producing a lot of EUV for a long time and getting a significant fraction (...like 1%) of the photons on the target is very hard.

Re: TSMC unveils 1.6nm process technology with backside power delivery

#144

Post by blagie »

1oooqooq wrote: post #136
blagie wrote: post #135

Earlier quoted context omitted.

The wafer is thick. Let's call it a mm thick (not quite, but close). Devices are tiny. The claim is 1.6nm, which isn't quite true, but let's pretend it is, since for the qualitative argument, it doesn't make a difference. That's on the order of a million times smaller than the thickness of the wafer. Historically, everything was etched, grown, deposited, and sputtered on one side of the wafer. The rest of the wafer w…

now I'm even more confused. why start with Si if you're going to put a glass layer before anything else? why not start with glass right away?

Ergo, the TL;DR :)

Even so, I oversimplified things a lot (a lot of the processes to leverage the silicon wafer, but some don't):

https://en.wikipedia.org/wiki/Silicon_on_insulator

One of the things to keep in mind is that a silicon wafer starts with a near-perfect silicon ingot crystal:

https://en.wikipedia.org/wiki/Monocrystalline_silicon

The level of purity and perfection there is a little bit crazy to conceive.

It's also worth noting how insanely tiny devices are. A virus is ≈100nm. DNA is 2nm diameter. We're at There are something like ≈100 billion transistors per IC for something like a high-end GPU, and a single failed transistor can destroy that fancy GPU. That's literally just a few atoms out-of-place or a few atoms of some pollutant.

The level of perfection needed is insane, and the processes which go into that are equally insane. We are making things on glass, but the glass has to be nearly perfect glass.

Re: TSMC unveils 1.6nm process technology with backside power delivery

#145

Post by baq »

simpsond wrote: post #142
black_puppydog wrote: post #131

Earlier quoted context omitted.

Stupid beginner question: is MTr/mm² really the right thing to be looking at? Shouldn't it be more like mm²/MTr ? This feels kind of like these weird "miles per gallon" units, when "gallons per mile" is much more useful...

200 million transistors per square millimeter. Gallons per mile only makes sense when you are talking about dragsters.

gallons per hundred miles make much more sense than that.

incidentally, this is the measure rest of the world is advertising, except usually in liters per 100km.

there's a good reason for this: comparisons linear instead of inversely proportional. 6l/100km is 50% better than 9l/100km. 30mpg vs 20mpg is... not as simple.

Re: TSMC unveils 1.6nm process technology with backside power delivery

#146

Post by Detrytus »

simpsond wrote: post #142
black_puppydog wrote: post #131

Earlier quoted context omitted.

Stupid beginner question: is MTr/mm² really the right thing to be looking at? Shouldn't it be more like mm²/MTr ? This feels kind of like these weird "miles per gallon" units, when "gallons per mile" is much more useful...

200 million transistors per square millimeter. Gallons per mile only makes sense when you are talking about dragsters.

Gallons per hundred miles would be more useful.

I guess it's a matter of approach. Europeans are traveling familiar, constant distances and worry about fuel cost. Americans just fill up their tank and worry how far they can go :)

Re: TSMC unveils 1.6nm process technology with backside power delivery

#147

Post by sgalloway »

ThinkBeat wrote: post #139

I am not sure I understand backside in this instance and the illustration in the article didn't entirely help. In general, at least in older time, one side of the CPU has all the nice pins on it, and the motherboard has a pincushion that the pins match nicely. At the top of the CPU you put a HUGE heatsink on it and off you go. In this configuration the power delivery must be via the pincushion, through some of the pi…

Here's a very good youtube video on the subject of backside power delivery I watched a few days ago. https://youtu.be/hyZlQY2xmWQ?si=JuXtzRy0U0onEzoe

Re: TSMC unveils 1.6nm process technology with backside power delivery

#148

Post by onepointsixC »

SilverBirch wrote: post #111
tgtweak wrote: post #50

A16 in 2027 vs Intel's 18A in full swing by 2026 feels like a miss on TMSCs behalf. This looks like an open door for fabless companies to try Intel's foundry service.

There are definitely going to be people taking a bet on the Intel foundry, but Intel has tried this before and it has worked badly.

Sounds like an easy short for you then.

Re: TSMC unveils 1.6nm process technology with backside power delivery

#149

Post by gosub100 »

The "Hollywood accounting" transistor density aside, I think a new metric needs to become mainstream: "wafers per machine per day" and "machines per year manufactured".

Getting these machines built and online is more important than what one machine (that might be less than 6 per year) can do.

The information, I'm sure, is buried in their papers, but I want to know what node processes are in products available now.

Re: TSMC unveils 1.6nm process technology with backside power delivery

#150

Post by Workaccount2 »

Sysreq2 wrote: post #95
Workaccount2 wrote: post #63

Earlier quoted context omitted.

Intel has a 1.4nm process in the pipeline for ~2027. They just took delivery on their first high NA EUV machine in order to start working on it. Their gamble however is that they need to figure out DSA, a long storied technology that uses self-forming polymers to allow less light to sharply etch smaller features. If they figure out DSA, they will likely be ahead of TSMC. If not, it will just be more very expensive la…

The nomenclature for microchip manufacturing left reality a couple generations ago. Intel’s 14A process is not a true 14A half-pitch. It’s kind of like how they started naming CPUs off “performance equivalents” instead of using raw clock speed. And this isn’t just Intel. TSMC, Samsung, everyone is doing half-pitch equivalent naming now a days. This is the industry roadmap from 2022: https://irds.ieee.org/images/files…

"Likely better" doesn't come from 14A vs 16A. It comes from Intel using High NA-EUV vs TSMC using double pattern Low NA-EUV.

If Intel pulls off DSA, they will be using a newer generation of technology compared to TSMC using an optimized older generation. Could TSMC still make better chips? Maybe. But Intel will likely be better.

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