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TSMC unveils 1.6nm process technology with backside power delivery

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Re: TSMC unveils 1.6nm process technology with backside power delivery

#131

Post by black_puppydog »

futureshock wrote: post #59

Comments about the marketing driven nm measurements aside, this still looks like another solid advance for TSMC. They are already significantly ahead of Samsung and Intel on transistor density. TSMC is at 197 MTr/mm2 wile Samsung is at 150 MTr/mm2 and Intel is at 123 MTr/mm2. This 1.6nm process will put them around 230 MTr/mm2 by 2026. When viewed by this metric, Intel is really falling behind.

Stupid beginner question: is MTr/mm² really the right thing to be looking at? Shouldn't it be more like mm²/MTr ? This feels kind of like these weird "miles per gallon" units, when "gallons per mile" is much more useful...

Re: TSMC unveils 1.6nm process technology with backside power delivery

#132

Post by merb »

7thpower wrote: post #87
ReptileMan wrote: post #65

Earlier quoted context omitted.

Not understanding chip design - but is it possible to get more computational bang with less transistors - are there some optimizations to be had? Better design that could compensate for bigger nodes?

Yes, generally one of the trends has been movement toward specialized coprocessors/accelerators. This was happening before the recent AI push and has picked up steam. If you think of an SOC, the chip in your phone, more and more of the real estate is being dedicated to specialized compute (AI accelerators, GPUs, etc. vs general purpose compute (CPU). At the enterprise scale, one of the big arguments NVIDIA has been m…

JavaScript accelerator would probably half the power consumption of the world. The problem is just, that as soon as it would have widespread usage it would probably already be too old.

Re: TSMC unveils 1.6nm process technology with backside power delivery

#133

Post by kumarvvr »

futureshock wrote: post #59

Comments about the marketing driven nm measurements aside, this still looks like another solid advance for TSMC. They are already significantly ahead of Samsung and Intel on transistor density. TSMC is at 197 MTr/mm2 wile Samsung is at 150 MTr/mm2 and Intel is at 123 MTr/mm2. This 1.6nm process will put them around 230 MTr/mm2 by 2026. When viewed by this metric, Intel is really falling behind.

Its so hard to even fathom 200+ Million Transistors in 1 square millimeter !

And, to think, it's all done with light !

We live in interesting times !

Re: TSMC unveils 1.6nm process technology with backside power delivery

#134

Post by audunw »

Havoc wrote: post #8

>1.6nm Gotta love how we now have fractions of a near meaningless metric.

The metric means what it has always meant: lower numbers mean higher transistor density on some area (the digital part) of the chip.

What more do you want? It’s as meaningful as a single number ever could be.

If you’re a consumer - if you don’t design chips - lower number means there’s some improvement somewhere. That’s all you need to know. It’s like horse powers on a car. The number doesn’t tell you everything about the performance under all conditions but it gives a rough idea comparatively speaking.

If you’re a chip designer then you never cared about the number they used in naming the process anyway. You would dig into the specification and design rules from the fab to understand the process. The “nm” number might show up in the design rules somewhere.. but that’s never been relevant to anyone, ever.

I really don’t understand why so many commenters feel the need to point out that “nm” doesn’t refer to a physical dimension. Who cares? It doesn’t have any impact on anyone. It’s very mildly interesting at best. It’s a near meaningless comment.

Re: TSMC unveils 1.6nm process technology with backside power delivery

#135

Post by blagie »

1oooqooq wrote: post #94
blagie wrote: post #35

Earlier quoted context omitted.

ELI5: ICs are manufactured on silicon disks called wafers. Discs have two sides, and traditionally, everything was done on top. We can now do power on the bottom. This makes things go faster and use less power: * Power wires are big (and can be a bit crude). The bigger the better. Signal wires are small and precise. Smaller is generally better. * Big wires, if near signal wires, can interfere with them working optima…

so the wafer is a huge ground plane? still can't see how one side is separate from the other if its the same block.

The wafer is thick. Let's call it a mm thick (not quite, but close). Devices are tiny. The claim is 1.6nm, which isn't quite true, but let's pretend it is, since for the qualitative argument, it doesn't make a difference. That's on the order of a million times smaller than the thickness of the wafer.

Historically, everything was etched, grown, deposited, and sputtered on one side of the wafer. The rest of the wafer was mostly mechanical support. The other side of the wafer is a universe away.

The world is more complex today, but that's a good model to keep in mind.

For a 3d integrated circuit, you would do this, and then e.g. grind away the whole wafer, and be left with a few micron thick sheet of just the electronics, which you'd mechanically place on top of another similar sheet. That's every bit as complex as it sounds. That's why this was restricted to very high-end applications.

As for whether the wafer is a huge ground plane, that's complex too, since it depends on the top of the device and the IC:

* First, it's worth remembering a pure silicon crystal is an insulator. It's only when you dope it that it becomes a conductor. The wafer starts out undoped.

* Early ICs had the whole wafer doped, and the collector of all the NPN transistors was just the wafer. There, it was a ground plane.

* SOI processes deposit a layer of glass on top of the wafer, and everything else on the glass. There, the wafer is insulated from the circuit.

So all of this can very quickly go in many directions, depending on generation of technology and application.

I'm not sure this post is helpful, since it's a lot of complexity in an ELI5, so I'll do a TL;DR: It's complicated. (or: Ask your dad)

Re: TSMC unveils 1.6nm process technology with backside power delivery

#136

Post by 1oooqooq »

blagie wrote: post #135
1oooqooq wrote: post #94

Earlier quoted context omitted.

so the wafer is a huge ground plane? still can't see how one side is separate from the other if its the same block.

The wafer is thick. Let's call it a mm thick (not quite, but close). Devices are tiny. The claim is 1.6nm, which isn't quite true, but let's pretend it is, since for the qualitative argument, it doesn't make a difference. That's on the order of a million times smaller than the thickness of the wafer. Historically, everything was etched, grown, deposited, and sputtered on one side of the wafer. The rest of the wafer w…

now I'm even more confused. why start with Si if you're going to put a glass layer before anything else? why not start with glass right away?

Re: TSMC unveils 1.6nm process technology with backside power delivery

#137

Post by spxneo »

audunw wrote: post #134
Havoc wrote: post #8

>1.6nm Gotta love how we now have fractions of a near meaningless metric.

The metric means what it has always meant: lower numbers mean higher transistor density on some area (the digital part) of the chip. What more do you want? It’s as meaningful as a single number ever could be. If you’re a consumer - if you don’t design chips - lower number means there’s some improvement somewhere. That’s all you need to know. It’s like horse powers on a car. The number doesn’t tell you everything abou…

what is a rough rule of thumb for each 1nm reduction? What does that increase in transistor density look like each year? If the jump is bigger (5nm->3nm), does that rate of change increase too?

trying to understand the economic impact of these announcements as I don't understand this topic well enough

Re: TSMC unveils 1.6nm process technology with backside power delivery

#138

Post by Denvercoder9 »

api wrote: post #27
blagie wrote: post #23

Earlier quoted context omitted.

Because it lost meaning somewhere between a micron and 100nm. From roughly the 1960s through the end of the 1990s, the number meant printed gate lengths or half-pitch (which were identical). At some point, companies started using "equivalences" which became increasingly detached from reality. If my 50nm node had better performance than your 30nm node because I have FinFETs or SOI or whatever, shouldn't I call mine 30…

The same thing happened with chip frequency around the end of the 1990s. Chip frequencies stagnated (end of Dennard scaling if I remember correctly) giving the impression that single threaded performance had stagnated, but since then chip makers have used increasing data and instruction parallelism to squeeze even more apparent single threaded performance out of chips. A 3ghz chip today is usually way faster on avera…

> The same thing happened with chip frequency around the end of the 1990s.

Not really the same thing, though. If I buy a chip that's advertised as 3.4GHz, it'll run at 3.4GHz. Maybe not all the time, but it'll achieve that speed. If I buy a chip advertised as being produced with a 3nm process, there's nothing even resembling 3nm on there.

Re: TSMC unveils 1.6nm process technology with backside power delivery

#139

Post by ThinkBeat »

I am not sure I understand backside in this instance and the illustration in the article didn't entirely help.

In general, at least in older time, one side of the CPU has all the nice pins on it, and the motherboard has a pincushion that the pins match nicely. At the top of the CPU you put a HUGE heatsink on it and off you go.

In this configuration the power delivery must be via the pincushion, through some of the pins.

Intuitively that sounds to me like the power is coming in the backside? But given that it is a big deal I am missing something.

Is the power fed from the "top" of the cpu where the heatsink would sit?

Re: TSMC unveils 1.6nm process technology with backside power delivery

#140

Post by kjkjadksj »

jjk166 wrote: post #125
ReptileMan wrote: post #65

Earlier quoted context omitted.

Not understanding chip design - but is it possible to get more computational bang with less transistors - are there some optimizations to be had? Better design that could compensate for bigger nodes?

The design optimization software for modern semiconductors is arguably the most advanced design software on earth with likely tens if not hundreds of millions of man-years put into it. It takes into account not only the complex physics that apply at the nano-scale but also the interplay of the various manufacturing steps and optimizes trillions of features. Every process change brings about new potential optimization…

What about the effect of heat? More transistors per area equate a hotter chip, no?
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