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TSMC unveils 1.6nm process technology with backside power delivery

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Re: TSMC unveils 1.6nm process technology with backside power delivery

#171

Post by satiric »

Detrytus wrote: post #146
simpsond wrote: post #142

Earlier quoted context omitted.

200 million transistors per square millimeter. Gallons per mile only makes sense when you are talking about dragsters.

Gallons per hundred miles would be more useful. I guess it's a matter of approach. Europeans are traveling familiar, constant distances and worry about fuel cost. Americans just fill up their tank and worry how far they can go :)

If I buy 2 gallons of gas, and my car gets 30 mpg, then I can go 60 miles. Doesn't seem that hard to me. Need the other way around? I need to go 100 miles. At 30 miles per gallon, that's a little over 3 gallons. This is simple mental math.

Re: TSMC unveils 1.6nm process technology with backside power delivery

#172

Post by whereismyacc »

AdamN wrote: post #78
blagie wrote: post #35

Earlier quoted context omitted.

ELI5: ICs are manufactured on silicon disks called wafers. Discs have two sides, and traditionally, everything was done on top. We can now do power on the bottom. This makes things go faster and use less power: * Power wires are big (and can be a bit crude). The bigger the better. Signal wires are small and precise. Smaller is generally better. * Big wires, if near signal wires, can interfere with them working optima…

There's still the question though of why they didn't do this decades ago - seems very obvious that this layout is better. What changed that made it possible only now and not earlier?

I assume the idea itself is pretty obvious, but the manufacturing techniques to actually implement it are complicated

Re: TSMC unveils 1.6nm process technology with backside power delivery

#173

Post by brennanpeterson »

Workaccount2 wrote: post #150
Sysreq2 wrote: post #95

Earlier quoted context omitted.

The nomenclature for microchip manufacturing left reality a couple generations ago. Intel’s 14A process is not a true 14A half-pitch. It’s kind of like how they started naming CPUs off “performance equivalents” instead of using raw clock speed. And this isn’t just Intel. TSMC, Samsung, everyone is doing half-pitch equivalent naming now a days. This is the industry roadmap from 2022: https://irds.ieee.org/images/files…

"Likely better" doesn't come from 14A vs 16A. It comes from Intel using High NA-EUV vs TSMC using double pattern Low NA-EUV. If Intel pulls off DSA, they will be using a newer generation of technology compared to TSMC using an optimized older generation. Could TSMC still make better chips? Maybe. But Intel will likely be better.

I am not sure where that would come from. There is nothing about dsa that means this.

Dsa is one of many patterning assist technologies, just...an old one. Neat, but not 'new'. You use patterning assist to make smaller, more regular features, which is exactly what the 16a vs 18a refers to.

That has somewhat less to do with performance, which is tied as much to material, stress, and interface parameters. Nothing gets better from being smaller in the post dennard scaling era, the work of integration is making better devices anyway.

Patterning choices imply different consequences. For example,.a.double euv integration can take advantage of spacer assists to reduce ler and actually improve cdu even with a double expose. Selective etch can improve bias, spacer trickery can create uniquely small regular features that cannot be done with single patterns. Conversely, overlay trees get bushier, and via CD variance can cause horrific electrical variance. It is complicated, history dependent, and everything is on the developmental edge.

Re: TSMC unveils 1.6nm process technology with backside power delivery

#174

Post by zeusk »

alberth wrote: post #158
futureshock wrote: post #59

Comments about the marketing driven nm measurements aside, this still looks like another solid advance for TSMC. They are already significantly ahead of Samsung and Intel on transistor density. TSMC is at 197 MTr/mm2 wile Samsung is at 150 MTr/mm2 and Intel is at 123 MTr/mm2. This 1.6nm process will put them around 230 MTr/mm2 by 2026. When viewed by this metric, Intel is really falling behind.

> This 1.6nm process will put them around 230 MTr/mm2 Would it be that x2 (for front & back)? E.g., 230 on front side and another 230 on back side = 460 MTr/mm2 TOTAL

BSPDN is not about putting devices on the front and back, the logic layer is still mostly 2D, it's about the power connects moving to the back of the chip so there's less interference with logic and larger wiring can be used.

Re: TSMC unveils 1.6nm process technology with backside power delivery

#175

Post by brennanpeterson »

blagie wrote: post #37
brennanpeterson wrote: post #24

Earlier quoted context omitted.

Half your wires deliver power, half deliver signal. So if you do both on the same side, you need twice the density of wires. If you split the delivery into two parts, you get double the density without needing to make things smaller.

This isn't quite right. Big wires (ideally entire planes) deliver power. Small wires deliver signal. Half and half isn't the right split, and you don't want to make power wires smaller. The very different requirements of the two is where a lot of the gains come in.

True! I went a little far in the name of 'eli5'. I think it roughly holds that you gain about a factor of 1.5 in routing density by removing the power distribution, so you can relax some critical patterning. But I havent looked closely in a long time.

Re: TSMC unveils 1.6nm process technology with backside power delivery

#176

Post by zeusk »

choilive wrote: post #141
merb wrote: post #132

Earlier quoted context omitted.

JavaScript accelerator would probably half the power consumption of the world. The problem is just, that as soon as it would have widespread usage it would probably already be too old.

I believe ARM has some instructions that is JavaScript specific so we're kinda in that direction already.

Back in the day, they supported byte code execution - https://en.wikipedia.org/wiki/Jazelle

Re: TSMC unveils 1.6nm process technology with backside power delivery

#177

Post by langsoul-com »

shookness wrote: post #79
HarHarVeryFunny wrote: post #74

Earlier quoted context omitted.

Intel is the one trying to catch up to TSMC, not vice versa! The link you give doesn't have any details of Intel's 18A process, including no indication of it innovating in any way, as opposed to TSMC with their "backside power delivery" which is going to be critical for power-hungry SOTA AI chips.

While you are correct that it is Intel trying to catch TSMC, you are wrong about the origin of backside power delivery. The idea originated at Intel sometime ago, but it would be very ironic if TSMC implements it before Intel...

Intel has been out of the game for so long. Their deadlines are just PR speak, in reality, they'd definitely run into Road blocks.

Not saying TSMC won't, but they have so much more experience in the cutting edge.

Re: TSMC unveils 1.6nm process technology with backside power delivery

#180

Post by robocat »

crote wrote: post #162
robocat wrote: post #151

Earlier quoted context omitted.

Reminiscent of the Java CPUs: Not even used for embedded (ironically the reason Java was created?). And not used at all by the massive Java compute needed for corporate software worldwide?

Weren't they used in Java Cards? Basically, every single credit card sized security chip (including actual credit cards, of course) is a small processor running Java applets. Pretty much everyone has one or more in their wallet. I'd assume those were actual Java CPUs directly executing bytecode?

> Weren't they used in Java Cards?

Not sure: https://en.wikipedia.org/wiki/Java_processor doesn't seem to mention any in current use. I am ignorant of the actual correct answer: I had simply presumed it is simpler to write the virtual machine using a commercial ISA than to develop a custom ISA.

  Java Card bytecode run by the Java Card Virtual Machine is a functional subset of Java 2 bytecode run by a standard Java Virtual Machine but with a different encoding to optimize for size.
https://en.wikipedia.org/wiki/Java_Card_OpenPlatform has some history but nothing jumped out to answer your question.
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