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TSMC unveils 1.6nm process technology with backside power delivery

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Re: TSMC unveils 1.6nm process technology with backside power delivery

#91

Post by smallmancontrov »

dmix wrote: post #82
bmicraft wrote: post #47

Earlier quoted context omitted.

Normally? That "standard" hasn't been used "normally" for 20 years now. Arguably the new way is normal in every sense of the word

Do you think they'll be advertising 0.9nm in the future or switch it up at some point?

I see MTr/mm2 a lot, it feels like a better measure, and it feels like the time is ripe for marketing to make a jump. Bigger is better, "mega" is cool, the numbers are hundreds to thousands in the foreseeable future so no chance of confusion with nm. What's not to love? But hey, I don't make these decisions, and I see no indication that anyone in a position to make these decisions has actually made them. Shrug.

Re: TSMC unveils 1.6nm process technology with backside power delivery

#92

Post by DSMan195276 »

AdamN wrote: post #78
blagie wrote: post #35

Earlier quoted context omitted.

ELI5: ICs are manufactured on silicon disks called wafers. Discs have two sides, and traditionally, everything was done on top. We can now do power on the bottom. This makes things go faster and use less power: * Power wires are big (and can be a bit crude). The bigger the better. Signal wires are small and precise. Smaller is generally better. * Big wires, if near signal wires, can interfere with them working optima…

There's still the question though of why they didn't do this decades ago - seems very obvious that this layout is better. What changed that made it possible only now and not earlier?

> seems very obvious that this layout is better

"Better" is relative, the layout introduces more fabrication steps so it's only better if you actually get some benefit from it. Decades ago designs didn't require as much power or have as many transistors to wire so it wasn't an issue.

Re: TSMC unveils 1.6nm process technology with backside power delivery

#94

Post by 1oooqooq »

blagie wrote: post #35
tvbv wrote: post #2

could someone ELi5 the backside power delivery please ?

ELI5: ICs are manufactured on silicon disks called wafers. Discs have two sides, and traditionally, everything was done on top. We can now do power on the bottom. This makes things go faster and use less power: * Power wires are big (and can be a bit crude). The bigger the better. Signal wires are small and precise. Smaller is generally better. * Big wires, if near signal wires, can interfere with them working optima…

so the wafer is a huge ground plane? still can't see how one side is separate from the other if its the same block.

Re: TSMC unveils 1.6nm process technology with backside power delivery

#95

Post by Sysreq2 »

Workaccount2 wrote: post #63
futureshock wrote: post #59

Comments about the marketing driven nm measurements aside, this still looks like another solid advance for TSMC. They are already significantly ahead of Samsung and Intel on transistor density. TSMC is at 197 MTr/mm2 wile Samsung is at 150 MTr/mm2 and Intel is at 123 MTr/mm2. This 1.6nm process will put them around 230 MTr/mm2 by 2026. When viewed by this metric, Intel is really falling behind.

Intel has a 1.4nm process in the pipeline for ~2027. They just took delivery on their first high NA EUV machine in order to start working on it. Their gamble however is that they need to figure out DSA, a long storied technology that uses self-forming polymers to allow less light to sharply etch smaller features. If they figure out DSA, they will likely be ahead of TSMC. If not, it will just be more very expensive la…

The nomenclature for microchip manufacturing left reality a couple generations ago. Intel’s 14A process is not a true 14A half-pitch. It’s kind of like how they started naming CPUs off “performance equivalents” instead of using raw clock speed. And this isn’t just Intel. TSMC, Samsung, everyone is doing half-pitch equivalent naming now a days.

This is the industry roadmap from 2022: https://irds.ieee.org/images/files/pdf/2022/2022IRDS_Litho.p... If you look at page 6 there is a nice table that kind of explains it.

Certain feature sizes have hit a point of diminishing returns, so they are finding new ways to increase performance. Each generation is better than the last but we have moved beyond simple shrinkage.

Comparing Intel’s 14A label to TSMCs 16A is meaningless without performance benchmarks. They are both just marketing terms. Like the Intel/AMD CPU wars. You can’t say one is better because the label says it’s faster. There’s so much other stuff to consider.

Re: TSMC unveils 1.6nm process technology with backside power delivery

#96

Post by sct202 »

shookness wrote: post #79
HarHarVeryFunny wrote: post #74

Earlier quoted context omitted.

Intel is the one trying to catch up to TSMC, not vice versa! The link you give doesn't have any details of Intel's 18A process, including no indication of it innovating in any way, as opposed to TSMC with their "backside power delivery" which is going to be critical for power-hungry SOTA AI chips.

While you are correct that it is Intel trying to catch TSMC, you are wrong about the origin of backside power delivery. The idea originated at Intel sometime ago, but it would be very ironic if TSMC implements it before Intel...

Intel is not the inventor of backside power, they are the first planning to commercialize it. It's similar to finfets and GAA where Intel or Samsung may be first to commercialize an implementation of those technologies, but the actual conceptual origin and first demonstrations are at universities or research consortiums like IMEC. Example Imec demonstrating backside power in 2019 https://spectrum.ieee.org/buried-power-lines-make-memory-fas... far before powerVia was announced.

Re: TSMC unveils 1.6nm process technology with backside power delivery

#97

Post by pjc50 »

ReptileMan wrote: post #65
futureshock wrote: post #59

Comments about the marketing driven nm measurements aside, this still looks like another solid advance for TSMC. They are already significantly ahead of Samsung and Intel on transistor density. TSMC is at 197 MTr/mm2 wile Samsung is at 150 MTr/mm2 and Intel is at 123 MTr/mm2. This 1.6nm process will put them around 230 MTr/mm2 by 2026. When viewed by this metric, Intel is really falling behind.

Not understanding chip design - but is it possible to get more computational bang with less transistors - are there some optimizations to be had? Better design that could compensate for bigger nodes?

Everyone generally does that before sending the design to the fab.

Not to say that improvements and doing more with less are impossible, they probably aren't, but it's going to require significant per design human effort to do that.

Re: TSMC unveils 1.6nm process technology with backside power delivery

#98

Post by exe34 »

_heimdall wrote: post #48
blackoil wrote: post #20

Earlier quoted context omitted.

Number represents transistor density. 2nm has ~twice the density of 4nm. If you ignore nm as unit of distance it makes sense.

They're using the wrong units if we need to consider the nanometer as something other than a measure of distance.

Wait till you talk to theoretical physicists who set c=h-bar=1.

Re: TSMC unveils 1.6nm process technology with backside power delivery

#99

Post by potatolicious »

ReptileMan wrote: post #65
futureshock wrote: post #59

Comments about the marketing driven nm measurements aside, this still looks like another solid advance for TSMC. They are already significantly ahead of Samsung and Intel on transistor density. TSMC is at 197 MTr/mm2 wile Samsung is at 150 MTr/mm2 and Intel is at 123 MTr/mm2. This 1.6nm process will put them around 230 MTr/mm2 by 2026. When viewed by this metric, Intel is really falling behind.

Not understanding chip design - but is it possible to get more computational bang with less transistors - are there some optimizations to be had? Better design that could compensate for bigger nodes?

Some yeah, but many of these optimizations aren't across-the-board performance improvements, but rather specializations that favor specific kinds of workloads.

There are the really obvious ones like on-board GPUs and AI accelerators, but even within the CPU you have optimizations that apply to specific kinds of workloads like specialized instructions for video encode/decode.

The main "issue", such as it is, is that this setup advantages vertically integrated players - the ones who can release software quickly to use these optimizations, or even going as far as to build specific new features on top of these optimizations.

For more open platforms you have a chicken-and-egg problem. Chip designers have little incentive to dedicate valuable and finite transistors to specialized computations if the software market in general hasn't shown an interest. Even after these optimizations/specialized hardware have been released, software makers often are slow in adopting them, resulting in consumers not seeing the benefit for a long time.

See for example the many years it took for Microsoft to even accelerate the rendering of Windows' core UI with the GPU.

Re: TSMC unveils 1.6nm process technology with backside power delivery

#100

Post by ano-ther »

Rinzler89 wrote: post #85
saganus wrote: post #69

Earlier quoted context omitted.

Do you know the name of the company that produces the EUV machine? is it ASML? It is my understanding that only ASML had cracked the EUV litography, but if there's another company out there, that would be an interesting development to watch.

>It is my understanding that only ASML had cracked the EUV litography Ackshually , EUV was cracked by Sandia Labs research in the US, with EUV light sources built by Cymer in the US. ASML was the only one allowed to license the tech and integrate it into their steppers after they bough Cymer in 2013. Hence why US has veto rights to whom Dutch based ASML can sell their EUV steppers to, as in not to China, despite ow m…

More on the history here:

https://www.asml.com/en/news/stories/2022/making-euv-lab-to-...

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