It would be incredible if AMD made some open source moves with their FPGAs as they did with their GPUs. That would allow open source tools like Yosys and nextptr to work with them easily vs. the painstaking reverse engineering efforts this now requires. Xilinx Vivado is a massive beast of a thing.
AMD announces the Spartan UltraScale+ FPGA family
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Re: AMD announces the Spartan UltraScale+ FPGA family
#62Earlier quoted context omitted.
In FPGAs you are literally programming the enablement of individual logic gates. That's it. There is no DMA or command ring, you have to implement it yourself. The FPGA bit code itself is extremely propertiary to each vendor as the nature of controlling all the logic sauces is all secret sauce. So you have to use the vendors tooling.
If we have to go thru a closed source or brain damaged hardware programming interface, this is a loss for us.
It has basically always been this way. Xilinx wasn't different before this announcement. Altera wasn't and isn't either. Some of the smaller lattice designs are a bit more open, but are a different market segment.
You will use Vivado and you will like it!
Re: AMD announces the Spartan UltraScale+ FPGA family
#63> Transceivers – Up to 8 GTH transceivers supporting up to 16.3 Gb/s Hey, the Spartan line is useful again!
Forgive my ignorance, and I made a brief attempt to answer it myself - what's GTH in this context?
Iirc it stands for “gigabit transceiver high speed” or something. There is also GTX, GTY, GTP, etc which are different implementations of SERDES on Xilinx chips.
It’s like USB full speed and USB high speed. They’re largely meaningless marketing terms just to differentiate generations.
Re: AMD announces the Spartan UltraScale+ FPGA family
#64It would be incredible if AMD made some open source moves with their FPGAs as they did with their GPUs. That would allow open source tools like Yosys and nextptr to work with them easily vs. the painstaking reverse engineering efforts this now requires. Xilinx Vivado is a massive beast of a thing. https://github.com/YosysHQ
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Re: AMD announces the Spartan UltraScale+ FPGA family
#65What are some killer apps for FPGAs? What major products do they enable?
Lower-volume specialty chips for interfaces (lots of I/O pins), such as adapters for an odd interface, custom hardware designs for which there isn't an existing chip, etc. For instance, audio, video or other signal processing can be done by putting the algorithm "directly" into the hardware design; it will run at a constant predictable speed thereafter.
RME realizes sub Firewire latencies over USB 2 with them in their audio interfaces, plus the ability to enable new functionalities via updates.
Re: AMD announces the Spartan UltraScale+ FPGA family
#66Earlier quoted context omitted.
Forgive my ignorance, and I made a brief attempt to answer it myself - what's GTH in this context?
Iirc it stands for “gigabit transceiver high speed” or something. There is also GTX, GTY, GTP, etc which are different implementations of SERDES on Xilinx chips. It’s like USB full speed and USB high speed. They’re largely meaningless marketing terms just to differentiate generations.
Thanks, that explains why all my search turned up was xilinx product materials...
Re: AMD announces the Spartan UltraScale+ FPGA family
#67What are some killer apps for FPGAs? What major products do they enable?
Deterministic latency so you know the upper bound and lower bound
Re: AMD announces the Spartan UltraScale+ FPGA family
#68What are some killer apps for FPGAs? What major products do they enable?
They are useful for products which do video encoding, decoding, and microwave receive and transmit of video data. They are useful for TCP/IP insertion and extraction of packet data, e.g., in video streams.
Re: AMD announces the Spartan UltraScale+ FPGA family
#69What are some killer apps for FPGAs? What major products do they enable?
I think we’re going to see a greatly increased use of FPGAs in AI applications. They can be very good at matrix multiplication. Think about an AI layer that tunes the FPGA based on incoming model requirements? Need an LPU like groq? Done. I would bet Apple Silicon gets some sort of FPGA in the neural engine.
Until you need floating point performance.
Re: AMD announces the Spartan UltraScale+ FPGA family
#70From the article "AMD Spartan UltraScale+ samples and evaluation kits are expected to be available for sampling and evaluation in the first half of 2025." For hardware products, what is the point of making these announcements a year in advance? Are they available for select partners before 2025?
Oh, yes. Hardware products and projects, specially those complex enough to need an FPGA, will usually have a long development pipeline and even one year seems pretty short.
And you can very often prototype with either an overpowered development board or you own prototype board with another FPGA, and then downsize appropriately as the project advances. Most importantly, if you know there will be a viable version in a year, you can postpone the final decision and Xilinx get to avoid having you choosing Altera now if it's possible that their new offering will match your project.