ASML and Samsung seal deal on 2nm chips • Hacker News Board

Re: ASML and Samsung seal deal on 2nm chips

#41

Post by Dalewyn » Sun, Dec 17, 2023, 1:03 AM UTC

phkahler wrote: post #7

Everything over the last years tells me we are very close to the end game in chip production. 1. power stopped scaling 2. clocks stopped - 4x over 20 years? 3. node names became fiction. 4. EUV now differentiates the top from everyone else. 5. IPC improvements are a trickle. 6. Tons of non-moores law ideas are here: A) GPUs B) chiplets C) stacked die D) specialized accelerators 7. Governments are now involved in divi…

Every time someone says we've hit peak microprocessing, we in fact have not hit peak microprocessing.

Re: ASML and Samsung seal deal on 2nm chips

#42

Post by nabla9 » Sun, Dec 17, 2023, 1:10 AM UTC

Atomic radius (average distance from the center to the outermost isolated electron) of copper 135pm, silicon 0.11pm.

2nm is 7 copper atoms or 9 silicon atoms.

Re: ASML and Samsung seal deal on 2nm chips

#43

Post by amelius » Sun, Dec 17, 2023, 1:11 AM UTC

HarHarVeryFunny wrote: post #10

Just for size reference, the SARS-CoV-2 (covid) virus is 100nm in diameter. A banana is 200,000,000nm, just in case you were wondering.

Bananas are radioactive, so better keep them away from the chips.

Re: ASML and Samsung seal deal on 2nm chips

#44

Post by mathematicaster » Sun, Dec 17, 2023, 1:20 AM UTC

iaseiadit wrote: post #37

ofrzeta wrote: post #26

Earlier quoted context omitted.

There's no (natural) law that prescribes that integers must be used, is it? Also, from what I understand that nanometer count is a bit symbolic, less literal. EDIT: for instance IMEC talks about "sub 1nm" process, that is 0.7nm ( https://www.tomshardware.com/news/imec-reveals-sub-1nm-trans... )

Going from 1 nm to 0.7 nm is hardly as impressive as going from 3 nm to 2 nm. It’s only 0.3 nm less!

(relative) size (still) matters!

Re: ASML and Samsung seal deal on 2nm chips

#45

Post by mathematicaster » Sun, Dec 17, 2023, 1:23 AM UTC

nabla9 wrote: post #42

Atomic radius (average distance from the center to the outermost isolated electron) of copper 135pm, silicon 0.11pm. 2nm is 7 copper atoms or 9 silicon atoms.

And for our next trick ... ... pattering to drive transistor switching rather than just transistor etching!

Re: ASML and Samsung seal deal on 2nm chips

#46

Post by nabla9 » Sun, Dec 17, 2023, 1:28 AM UTC

mathematicaster wrote: post #45

nabla9 wrote: post #42

Atomic radius (average distance from the center to the outermost isolated electron) of copper 135pm, silicon 0.11pm. 2nm is 7 copper atoms or 9 silicon atoms.

And for our next trick ... ... pattering to drive transistor switching rather than just transistor etching!

Single-atom transistor https://en.wikipedia.org/wiki/Single-atom_transistor

Re: ASML and Samsung seal deal on 2nm chips

#47

Post by 2OEH8eoCRo0 » Sun, Dec 17, 2023, 1:31 AM UTC

JB_Dev wrote: post #39

phkahler wrote: post #7

Everything over the last years tells me we are very close to the end game in chip production. 1. power stopped scaling 2. clocks stopped - 4x over 20 years? 3. node names became fiction. 4. EUV now differentiates the top from everyone else. 5. IPC improvements are a trickle. 6. Tons of non-moores law ideas are here: A) GPUs B) chiplets C) stacked die D) specialized accelerators 7. Governments are now involved in divi…

I used to agree with you until I saw this presentation by Jim Keller, one of the biggest names in chip architecture. It really illustrates how many more options we have to improve performance. https://www.youtube.com/live/oIG9ztQw2Gc?si=vCBGGm0tkhG-VOyd

I like that one. Building a chip involves many different manufacturing steps, each of which has room for improvement. I liked how he even mentions that advances in sandpaper allow us to make better chips.

Re: ASML and Samsung seal deal on 2nm chips

#48

Post by nabakin » Sun, Dec 17, 2023, 1:35 AM UTC

ofrzeta wrote: post #26

iaseiadit wrote: post #24

Earlier quoted context omitted.

You joke but it does seem like we’re near the end of the line. We can go from 3 nm to 2 nm to 1 nm, but we can’t go negative nanometers. That’s it.

There's no (natural) law that prescribes that integers must be used, is it? Also, from what I understand that nanometer count is a bit symbolic, less literal. EDIT: for instance IMEC talks about "sub 1nm" process, that is 0.7nm ( https://www.tomshardware.com/news/imec-reveals-sub-1nm-trans... )

They are joking too

Re: ASML and Samsung seal deal on 2nm chips

#49

Post by 2OEH8eoCRo0 » Sun, Dec 17, 2023, 1:36 AM UTC

iaseiadit wrote: post #24

gjm11 wrote: post #13

Nigel Tufnel, chief scientist at TSMC, explains the merits of the latest hardware from ASML: "This is a fab, but it's very special because if you can see, the numbers all go down to 2nm. Look, right across the board. 2nm, 2nm, 2nm, 2nm ..." "And most of the fabs go down to 3." "Exactly." "Does that mean it's ... smaller? Is it any smaller?" "Well, it's one smaller, isn't it? It's not 3. You see, most fabs are going t…

You joke but it does seem like we’re near the end of the line. We can go from 3 nm to 2 nm to 1 nm, but we can’t go negative nanometers. That’s it.

0.5nm, 0.25nm, 0.125nm ...

Re: ASML and Samsung seal deal on 2nm chips

#50

Post by kittoes » Sun, Dec 17, 2023, 1:41 AM UTC

gjm11 wrote: post #13

Nigel Tufnel, chief scientist at TSMC, explains the merits of the latest hardware from ASML: "This is a fab, but it's very special because if you can see, the numbers all go down to 2nm. Look, right across the board. 2nm, 2nm, 2nm, 2nm ..." "And most of the fabs go down to 3." "Exactly." "Does that mean it's ... smaller? Is it any smaller?" "Well, it's one smaller, isn't it? It's not 3. You see, most fabs are going t…

I know you just, but the numbers being so small makes a full decrement all that more impressive; 3 -> 2 is equivalent to 6 -> 4, 9 -> 6, 12 -> 8, ...