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ASML and Samsung seal deal on 2nm chips

koreaherald.com

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Re: ASML and Samsung seal deal on 2nm chips

#11

Post by huijzer »

phkahler wrote: post #7

Everything over the last years tells me we are very close to the end game in chip production. 1. power stopped scaling 2. clocks stopped - 4x over 20 years? 3. node names became fiction. 4. EUV now differentiates the top from everyone else. 5. IPC improvements are a trickle. 6. Tons of non-moores law ideas are here: A) GPUs B) chiplets C) stacked die D) specialized accelerators 7. Governments are now involved in divi…

Depends what you consider as part of chip production. If you consider new instructions and the related software as new chip production, then the performance improvements have continued quite dramatically. Single chip inference has gone 1000x over the last 10 years according to Bill Dally from Nvidia [1] at 10 minutes (probably not original source). Main gains according to the video have been different numeric types (fp16 for example) and more specialised hardware together with more complex instructions. Note that process improvements have only caused a 2.5x from that 1000x. He also mentions that Google‘s TPU has no fundamental benefit over dedicated instructions in GPUs. Quite an interesting video IMO.

[1]: https://youtu.be/kLiwvnr4L80

Re: ASML and Samsung seal deal on 2nm chips

#12

Post by huytersd »

HarHarVeryFunny wrote: post #10

Just for size reference, the SARS-CoV-2 (covid) virus is 100nm in diameter. A banana is 200,000,000nm, just in case you were wondering.

Just for completeness, “2nm” is more like 12-45nm actual transistor size. So on average about 5 of these transistors could fit inside a single SARS-CoV-2 viron.

Re: ASML and Samsung seal deal on 2nm chips

#13

Post by gjm11 »

Nigel Tufnel, chief scientist at TSMC, explains the merits of the latest hardware from ASML:

"This is a fab, but it's very special because if you can see, the numbers all go down to 2nm. Look, right across the board. 2nm, 2nm, 2nm, 2nm ..."

"And most of the fabs go down to 3."

"Exactly."

"Does that mean it's ... smaller? Is it any smaller?"

"Well, it's one smaller, isn't it? It's not 3. You see, most fabs are going to be running at 3. You're on 3 on your fab -- where can you go from there? Where?"

"I dunno."

"Nowhere, exactly. And what we do is, if we need that extra push over the cliff, you know what we do?"

"Put it down to 2."

"2. Exactly. One smaller."

Re: ASML and Samsung seal deal on 2nm chips

#14

Post by kaycebasques »

Just read this in Chip War (p. 333) by Chris Miller:

> Gelsinger has cut a deal with ASML to let Intel acquire the first next-generation EUV machine, which is expected to be ready in 2025. If Intel can learn how to use these new tools before rivals, it could provide a technological edge.

Is the book talking about the same tech or different? If the same, does it mean that Intel only gets a year or two of headstart?

Re: ASML and Samsung seal deal on 2nm chips

#15

Post by tomcam »

gjm11 wrote: post #13

Nigel Tufnel, chief scientist at TSMC, explains the merits of the latest hardware from ASML: "This is a fab, but it's very special because if you can see, the numbers all go down to 2nm. Look, right across the board. 2nm, 2nm, 2nm, 2nm ..." "And most of the fabs go down to 3." "Exactly." "Does that mean it's ... smaller? Is it any smaller?" "Well, it's one smaller, isn't it? It's not 3. You see, most fabs are going t…

> Nigel Tufnel

Deep cut

Re: ASML and Samsung seal deal on 2nm chips

#16

Post by tromp »

gjm11 wrote: post #13

Nigel Tufnel, chief scientist at TSMC, explains the merits of the latest hardware from ASML: "This is a fab, but it's very special because if you can see, the numbers all go down to 2nm. Look, right across the board. 2nm, 2nm, 2nm, 2nm ..." "And most of the fabs go down to 3." "Exactly." "Does that mean it's ... smaller? Is it any smaller?" "Well, it's one smaller, isn't it? It's not 3. You see, most fabs are going t…

Nice Spinal Tap parody...

[1] https://en.wikipedia.org/wiki/Up_to_eleven

Re: ASML and Samsung seal deal on 2nm chips

#17

Post by smoldesu »

tomcam wrote: post #15
gjm11 wrote: post #13

Nigel Tufnel, chief scientist at TSMC, explains the merits of the latest hardware from ASML: "This is a fab, but it's very special because if you can see, the numbers all go down to 2nm. Look, right across the board. 2nm, 2nm, 2nm, 2nm ..." "And most of the fabs go down to 3." "Exactly." "Does that mean it's ... smaller? Is it any smaller?" "Well, it's one smaller, isn't it? It's not 3. You see, most fabs are going t…

> Nigel Tufnel Deep cut

"Nigel gave me a drawing that said 2nm. Your understanding of pitch width and packaging technology is not my problem. I do what I'm told."

Re: ASML and Samsung seal deal on 2nm chips

#18

Post by layer8 »

colechristensen wrote: post #8
phkahler wrote: post #7

Everything over the last years tells me we are very close to the end game in chip production. 1. power stopped scaling 2. clocks stopped - 4x over 20 years? 3. node names became fiction. 4. EUV now differentiates the top from everyone else. 5. IPC improvements are a trickle. 6. Tons of non-moores law ideas are here: A) GPUs B) chiplets C) stacked die D) specialized accelerators 7. Governments are now involved in divi…

I'm guessing we're not done, we're just reaching the endgame with silicon dies. Next steps will be new tech sometimes with a long lead time until it has been developed to the extent that it's competitive with silicon. Things like integrated photonics (or a completely photonic CPU), quantum computers, or diamond instead of silicon (or other materials instead of silicon). Are we not still getting exponential growth in…

It's impossible for growth to be exponential indefinitely. Eventually it'll end up as a sigmoid curve.

Secondly, progress isn't smooth. It comes in phases and leaps, and it's possible for it to stagnate for a long time.

Re: ASML and Samsung seal deal on 2nm chips

#19

Post by jiggawatts »

Just to head off the inevitable comments about how 2nm isn't really 2nm: yes, we know, it's just a convention in the industry to indicate relative performance. It's basically a marketing term, more than anything else.

The numbers VLSI engineers actually care about are things like millions of transistors per square millimeter (MTr/mm^2), power per bit in picojoules (pJ), transistor rise times in nanoseconds, etc...

In those metrics, steady gains have been made, it's just that the actual component sizes haven't matched up to the gains recently. Instead, new types of technologies like "gate-all-around" have been used to eke out more performance instead of simply shrinking everything proportionally.

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