Die Area of only 3.84mm2 for Core + L2. This is a similar to Apple A14/A15. On TSMC N5 although they are likely different variant, optimising for clockspeed rather than Low Power. 13% increase in IPC, and additional clock speed increase as well from N5. The server variant Zen4C with 128 Core per socket should compete fairly well with Ampere ARM variant. I just hope AMD is a little more ambitious than they were and bo…
If that's even close to right, that should really start to shine when they have mobile APUs shipping.