I looked at the Mega65 with its three (not quite) 6502 CPU variants and I just found it so weird. Basically no 16 bit operations, instead a couple of 32 bit operations. Z register is no longer 0 and you have to set it non-zero to change bank configuration. Five instructions (nine bytes) to change bank and I do not understand how you can save the previous bank setting in case you want to restore it.
If you move the stack or zero page, the well known trick of using absolute plus index register no longer works the same as on the 6502 (breaking existing code). Sure, you could hardcode a different page, but the point of moving the stack is (probably) so you could do multi-tasking. But if processes are given different stack pages, they can no longer share code (if using such well known tricks in the code).
Moving zero page is in 256 steps, so you cannot use it as a movable stack frame (the 65816 can set it to any location in the first 64K).
I know there is a lot of interest in the Mega65, but I found it had so many poorly made design decisions that made me want to stay far away.
So far I find the 65816 to a well designed 16 bits ISA (I am also familiar with PDP-11, MSP430, MELPS7700 and Motorola 6812) that gives a lot of 6502 vibes, but is just a lot better. There are a couple of odd corners, probably due to the opcode space as you mention, but I would not call it a bunch of compromises.