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MIPS Becomes RISC-V

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Re: MIPS Becomes RISC-V

#171

Post by pabs3 »

Fordec wrote: post #59
MaxBarraclough wrote: post #36

Everyone's right to celebrate the success of RISC-V, but part of me thinks it's a shame that there's relatively little architectural diversity ( edit I should have said ISA diversity ) in modern CPUs. MIPS, Alpha, and Super-H, have all but faded away. Power/PowerPC is still out there somewhere though. Apparently they're still working on SPARC, too. [0] At least we'll always have the PS2. ...until the last one breaks,…

We need diversity for solving different problems, not for diversity sake. What problem did MIPS solve in a unique way that others didn't? Because it wasn't desktop, mobile, embedded, graphics or AI.

ISA diversity can surface bugs in code, that only shows up in ISAs with different approaches. For example code that works on some arches but is slow due to alignment issues will just fail to run on other arches.

Re: MIPS Becomes RISC-V

#172

Post by purpmint008 »

inkyoto wrote: post #143
retrac wrote: post #84

Earlier quoted context omitted.

That's how IBM implemented the AS/400 platform. Everything compiled down to a processor-agnostic bytecode that was the "binary" format. That IR was translated to native code for the underlying processor architecture as the final step. And objects contained both the IR and the native code. If you moved a binary to another host CPU, it would be retranslated and run automatically. The migration to POWER as the underlyin…

App uploads to the iOS store in the LLVM's own Bitcode format is a distant echo of the CPU ISA agnostic IR approach IBM employed at the time. Bitcode is transpiled down to the underlying CPU instructions via the static binary translation and optimisation, and the translation between Bitcode -> x86 or Bitcode -> ARM has been possible to do for some time: https://www.highcaffeinecontent.com/blog/20190518-Translatin...…

> their habit of obsoleting certain things fast

Lately, Google and Microsoft have been beating them at that ugly game.

Re: MIPS Becomes RISC-V

#173

Post by pabs3 »

arnd wrote: post #124
pacman2 wrote: post #119

Loongson still does MIPS. They are a little bit vaporware, even hard to get in China. https://en.wikipedia.org/wiki/Loongson

The next "loongarch" generation was already announced to move away from mips as the underlying ISA but instead allow running mips, arm64, risc-v, and x86 code in hardware assisted emulation.

A link about Loongarch:

https://www.zhihu.com/question/414069789

Re: MIPS Becomes RISC-V

#174

Post by bnjms »

genmud wrote: post #162
dfox wrote: post #127

Earlier quoted context omitted.

It is not that way today but for a long time the entry-level Cisco IOS router was PowerPC based, while the highend was invariably MIPS. On the other hand both architectural choices had nothing to do with the architecture and everything to do with choice of usable SoCs for that particular application (with Motorola/Freescale/NXP's "m68k Cisco router/Sun2 on a chip" SoCs being somewhat ironic in this regard).

I wouldn't consider cisco to be a tech-forward company or look to them as the barometer to where the networking industry is headed. Most of Broadcoms stuff is ARM based now, which is what most folks are putting in white label switches.

Fwiw, Broadcom is also what’s going into Cisco routers. Which supports your point.

Re: MIPS Becomes RISC-V

#175

Post by guerrilla »

brucehoult wrote: post #160
monocasa wrote: post #87

Earlier quoted context omitted.

Academic RISC was designed by Patterson and Hennessy. Hennessy went off and was one of the founders of MIPS, Patterson is one of the instrumental leaders in the RISC-V space.

Patterson and Hennessy were in competition with each other, at different universities. It's only much later they wrote text books together. Patterson says RISC-V is derived from RISC-I and RISC-II. I think this doesn't really old water -- at least no more so than any other RISC. RISC-I and RISC-II had condition codes and register windows, like SPARC. RISC-V doesn't have either, like MIPS. The RISC-V assembly language…

Nice that there's both MIPS and RISC-V versions of the book:

https://www.amazon.com/Computer-Organization-Design-MIPS-Arc...

https://www.amazon.com/Computer-Organization-Design-RISC-V-A...

I guess as of today we know which one to get.

Re: MIPS Becomes RISC-V

#176

Post by mokus »

TorKlingberg wrote: post #122
hamburglar wrote: post #113

Earlier quoted context omitted.

- the NOP instruction is 0x0 :)

I don't know if MIPS is the same, but I worked on an other architecture where NOP is 0x0, and it had an interesting effect. If you called an uninitialized function pointer, and it happened to point into zero:ed out memory, the CPU would execute NOPs for a good while until it hit something else. If that something else was code, it would start executing some function from the start, but with garbage arguments. It would…

AVR does this. I can attest to the “interesting” debugging...

Re: MIPS Becomes RISC-V

#177

Post by paulburton »

TorKlingberg wrote: post #122
hamburglar wrote: post #113

Earlier quoted context omitted.

- the NOP instruction is 0x0 :)

I don't know if MIPS is the same, but I worked on an other architecture where NOP is 0x0, and it had an interesting effect. If you called an uninitialized function pointer, and it happened to point into zero:ed out memory, the CPU would execute NOPs for a good while until it hit something else. If that something else was code, it would start executing some function from the start, but with garbage arguments. It would…

nanoMIPS (the last compressed MIPS ISA that sadly never made it across the whole product line) re-encoded nop(32) for much the same reason.

Re: MIPS Becomes RISC-V

#178

Post by paulburton »

rwmj wrote: post #33
zokier wrote: post #20

The progression of headlines is funny: 1) MIPS Strikes Back: 64-bit Warrior I6400 Arrives https://news.ycombinator.com/item?id=8258092 We are still in the game 2) Linux-running MIPS CPU available for free to universities – full Verilog code https://news.ycombinator.com/item?id=9444567 Okay, we are not doing so great, maybe we can get young kids hooked? 3) MIPS Goes Open Source https://news.ycombinator.com/item?id=187…

I have one of the purple MIPS SBCs from back when MIPS was briefly owned by Imagination ( https://en.wikipedia.org/wiki/Imagination_Creator https://elinux.org/MIPS_Creator_CI20 ). Slow as hell even back in 2014. I wonder if one day it'll be a museum piece :-?

At least you have a purple one - they were a lot better than their green forebears :)

Re: MIPS Becomes RISC-V

#179

Post by rayiner »

brucehoult wrote: post #137

In 2010 MIPS wanted $2 million from Berkeley to allow them to use the MIPS instruction encodings for processor cores that Berkeley would design entirely themselves. So they made up their own encodings instead. The rest is history. In many ways modern MIPS and RISC-V are pretty much just different binary encodings of the same ideas. [this was already posted as a comment in a thread, but on reflection it probably deser…

Off topic, but good morning! (From a lurker on the #Dylan IRC oh 15 years ago...) Great to see you're doing Risc-V compiler stuff now.
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