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MIPS Becomes RISC-V

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Re: MIPS Becomes RISC-V

#121

Post by cptskippy »

MaxBarraclough wrote: post #36

Everyone's right to celebrate the success of RISC-V, but part of me thinks it's a shame that there's relatively little architectural diversity ( edit I should have said ISA diversity ) in modern CPUs. MIPS, Alpha, and Super-H, have all but faded away. Power/PowerPC is still out there somewhere though. Apparently they're still working on SPARC, too. [0] At least we'll always have the PS2. ...until the last one breaks,…

> part of me thinks it's a shame that there's relatively little architectural diversity

Perhaps CPU diversity is in decline but it seems to me that the industry as a whole is moving towards more diversity. It's gotten significantly cheaper to roll your own chips to the point that we've seen entirely new processors emerging (e.g. GPUs, TPUs, etc) and becoming commonplace if not essential.

Isn't the point of RISC-V that the CPU is simple and augmented or complimented by any number of custom co-processors? If this is the general tend in the industry then the CPU itself might become a commodity part to be easily swapped out as something better emerges. Particularly if it can be abstracted away from the ISA.

Re: MIPS Becomes RISC-V

#122

Post by TorKlingberg »

hamburglar wrote: post #113
musicale wrote: post #91

There's a lot to like about MIPS. It's a perfectly usable RISC architecture that: - is easy to implement - is supported by Debian, gcc, etc.. - is virtualizable - scales from embedded systems (e.g. compressed MIPS16 ISA) up to huge shared-memory multiprocessor systems with hundreds of CPUs Like RISC-V, MIPS traces its lineage to the dawn of the RISC revolution in the 1980s, though on the Hennessy/Stanford side rather…

- the NOP instruction is 0x0 :)

I don't know if MIPS is the same, but I worked on an other architecture where NOP is 0x0, and it had an interesting effect. If you called an uninitialized function pointer, and it happened to point into zero:ed out memory, the CPU would execute NOPs for a good while until it hit something else. If that something else was code, it would start executing some function from the start, but with garbage arguments. It would often get quite far in and several functions calls down before something crashed. Made for fun stack traces and interesting debugging :-)

Re: MIPS Becomes RISC-V

#123

Post by jacquesm »

elihu wrote: post #74
MaxBarraclough wrote: post #36

Everyone's right to celebrate the success of RISC-V, but part of me thinks it's a shame that there's relatively little architectural diversity ( edit I should have said ISA diversity ) in modern CPUs. MIPS, Alpha, and Super-H, have all but faded away. Power/PowerPC is still out there somewhere though. Apparently they're still working on SPARC, too. [0] At least we'll always have the PS2. ...until the last one breaks,…

I wish the barriers to using new architectures were lower. For instance, suppose binaries were typically distributed in a platform-agnostic format, like LLVM intermediate representation or something equivalent. When you run your program the first time, it's compiled to native code for your architecture and cached for later use. I realize I've sort of just re-invented Javascript. But what if we just did away with nati…

> I realize I've sort of just re-invented Javascript.

You've re-invented UCSD P-code.

https://en.wikipedia.org/wiki/P-code_machine

Re: MIPS Becomes RISC-V

#124

Post by arnd »

pacman2 wrote: post #119

Loongson still does MIPS. They are a little bit vaporware, even hard to get in China. https://en.wikipedia.org/wiki/Loongson

The next "loongarch" generation was already announced to move away from mips as the underlying ISA but instead allow running mips, arm64, risc-v, and x86 code in hardware assisted emulation.

Re: MIPS Becomes RISC-V

#125

Post by arnd »

esturk wrote: post #116
ChuckMcM wrote: post #41

It was unclear if "v8" of the MIPS architecture is a re-branded RISC-V or if v8 MIPS is a combined RISC-V + MIPS or what.

"In this context, the “8th generation” refers to seven generations of the traditional MIPS architecture, followed by an upcoming RISC-V design. It sounds like the company is implying that this is a smooth transition with some level of compatibility between the old and the new. It isn’t. It’s a clean break as the company switches from the old CPU design, that it owned, to a new one that’s in the public domain."

Mips R6 (Warrior m62xx/i6400/i6500/p6600) was already somewhat incompatible with R5 and earlier, the seventh generation nanomips i7200 was incompatible with that again.

Re: MIPS Becomes RISC-V

#126

Post by [deleted] »

projektfu wrote: post #52
rst wrote: post #22

Earlier quoted context omitted.

Depends where you look. Hard to see IBM's z/Architecture dying out in that timeframe (the latest branding for S/360-derived mainframes), for example, and the embedded space is likely to remain an odd bestiary for quite some time.

Isn't z/Architecture just emulated on top of POWER? That's been my impression for a while.

[deleted]

Re: MIPS Becomes RISC-V

#127

Post by dfox »

makomk wrote: post #103
slezyr wrote: post #88

Earlier quoted context omitted.

Check your router's CPU. I own 4 routers and all of them use MIPS. RISC-V is more like Graphene, it's yet to leave the lab.

Home routers used to be one of the last holdouts of MIPS, but all the modern ones have been switching to ARM. It's pretty much on its last legs there aside from the really cheap, low-end stuff.

It is not that way today but for a long time the entry-level Cisco IOS router was PowerPC based, while the highend was invariably MIPS. On the other hand both architectural choices had nothing to do with the architecture and everything to do with choice of usable SoCs for that particular application (with Motorola/Freescale/NXP's "m68k Cisco router/Sun2 on a chip" SoCs being somewhat ironic in this regard).

Re: MIPS Becomes RISC-V

#128

Post by arnd »

pwdisswordfish0 wrote: post #45
buescher wrote: post #12

"Development of the MIPS processor architecture has now stopped" Is anyone still developing SPARC?

Gaisler and the ESA are launching SPARC into space. https://www.gaisler.com/index.php/products/components/gr740

They are using risc-v for their 64-bit cores now.

Re: MIPS Becomes RISC-V

#129

Post by TheRealSteel »

elihu wrote: post #74
MaxBarraclough wrote: post #36

Everyone's right to celebrate the success of RISC-V, but part of me thinks it's a shame that there's relatively little architectural diversity ( edit I should have said ISA diversity ) in modern CPUs. MIPS, Alpha, and Super-H, have all but faded away. Power/PowerPC is still out there somewhere though. Apparently they're still working on SPARC, too. [0] At least we'll always have the PS2. ...until the last one breaks,…

I wish the barriers to using new architectures were lower. For instance, suppose binaries were typically distributed in a platform-agnostic format, like LLVM intermediate representation or something equivalent. When you run your program the first time, it's compiled to native code for your architecture and cached for later use. I realize I've sort of just re-invented Javascript. But what if we just did away with nati…

Isn't that basically what Android Runtime does?

Re: MIPS Becomes RISC-V

#130

Post by yjftsjthsd-h »

capableweb wrote: post #68
yjftsjthsd-h wrote: post #62

Earlier quoted context omitted.

Throwing out diversity because you don't see any immediate benefit is a great way to not have it when a different problem does show up. I don't know about unique way, but MIPS certainly was good at embedded; there's plenty of networking gear using it.

> MIPS certainly was good at embedded As far as I understand, it's not that MIPS is the best at embedded, it's just that it's cheaper to sell as the license cost is non-existing and good support already exists in kernels and so on.

> it's not that MIPS is the best at embedded, it's just that it's cheaper to sell

That sounds a lot like MIPS being the best at embedded. Not high-end, sure, but a lot of embedded is "what is the cheapest processor that can run Linux?"

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