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MIPS Becomes RISC-V

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Re: MIPS Becomes RISC-V

#51

Post by UncleOxidant »

mortenjorck wrote: post #5

This is more or less analogous to Blackberry moving to Android, isn’t it? Storied, old-guard tech company loses most of its market share, trades in its first-party stack for a rising open-source alternative. Is MIPS still a big enough name to make this much of a coup for RISC-V? Or is this the last-ditch effort of a fallen star of the semi market?

> Is MIPS still a big enough name to make this much of a coup for RISC-V?

No, not at this point. RISC-V already has plenty of momentum without this. The only thing that might change that analysis is if MIPS has some architecture patents that they could leverage to get some kind of RISC-V performance advantage. But I doubt they have anything like that now. And it's not like they have a stable of CPU designers that are now going to be switched from working on MIPS to working on RISC-V - they likely haven't had any of those folks working there since the 90s.

Re: MIPS Becomes RISC-V

#52

Post by projektfu »

rst wrote: post #22
gautamcgoel wrote: post #4

This is huge. It looks like the only architectures widely-deployed in ten years will be x86, ARM, Power, and RISC-V (maybe also SPARC64 in Japan, although that's rare in the US).

Depends where you look. Hard to see IBM's z/Architecture dying out in that timeframe (the latest branding for S/360-derived mainframes), for example, and the embedded space is likely to remain an odd bestiary for quite some time.

Isn't z/Architecture just emulated on top of POWER? That's been my impression for a while.

Re: MIPS Becomes RISC-V

#53

Post by dralley »

MaxBarraclough wrote: post #36

Everyone's right to celebrate the success of RISC-V, but part of me thinks it's a shame that there's relatively little architectural diversity ( edit I should have said ISA diversity ) in modern CPUs. MIPS, Alpha, and Super-H, have all but faded away. Power/PowerPC is still out there somewhere though. Apparently they're still working on SPARC, too. [0] At least we'll always have the PS2. ...until the last one breaks,…

I'm curious if someone could explain the architectural differences between ppc64le and aarch64? I've always heard they are quite similar.

Re: MIPS Becomes RISC-V

#55

Post by dv_dt »

zokier wrote: post #20

The progression of headlines is funny: 1) MIPS Strikes Back: 64-bit Warrior I6400 Arrives https://news.ycombinator.com/item?id=8258092 We are still in the game 2) Linux-running MIPS CPU available for free to universities – full Verilog code https://news.ycombinator.com/item?id=9444567 Okay, we are not doing so great, maybe we can get young kids hooked? 3) MIPS Goes Open Source https://news.ycombinator.com/item?id=187…

I had to do a quick context switch to make sure by ISA they meant Instruction Set Architecture not Industry Standard Architecture (ISA Bus)...

Re: MIPS Becomes RISC-V

#56

Post by sujayakar »

dragontamer wrote: post #19
londons_explore wrote: post #14

Earlier quoted context omitted.

SIMD today is only really helpful with a few usecases. If you want to encode some video, decode some jpegs, or do a physics simulation quicker, it's really going to help. It won't boot Linux any quicker tho. I suspect for consumer uses, SIMD is already used for nearly all the use cases it can be.

Are you sure about that? The original SIMD-papers in the 1980s show how to compile a Regex into a highly-parallel state machine and then "reduced" (aka: Scan / Prefix-operation: https://en.wikipedia.org/wiki/Prefix_sum ). A huge amount of operations, such as XML-whitespace removal (aka: SIMD Steam Compacting), Regular Expressions, and more, have been proven ~30 to 40 years ago to benefit from SIMD compute. Yet such l…

I'm very interested in this space! I've been hacking on some open-source libraries around these ideas: rsdict [1], a SIMD-accelerated rank/select bitmap data structure, and arbolito [2], a SIMD-accelerated tiny trie.

For rsdict, the main idea is to use `pshufb` to implement querying a lookup table on a vector of integers and then use `psadbw` to horizontally sum the vector.

The arbolito code is a lot less fleshed out, but the main idea is to take a small trie and encode it into SIMD vectors. Laying out the nodes into a linear order, we'd have one vector that maintains a parent pointer (4 bits for 16 node trees in 128-bit vectors) and another vector with the incoming edge label.

Then, following the Teddy algorithm[3] (very similar to the Hillis/Stele state transition ideas too!), we can implement traversing the tree as a state machine, where each node in the trie has a bitmask, and the state transition is a parallel bitshift + shuffle of parent state to children states + bitwise AND. We can even reduce the circuit depth of this algorithm to `O(log depth)` by using successive squaring of the transition, like Hillis/Steele describe too.

I've put it on the backburner, but my main goal for arbolito would be to find a way to stitch together these "tiny tries" into a general purpose trie adaptively and get query performance competitive with a hashmap for integer keys. The ART paper[4] does similar stuff but without the SIMD tricks.

[1] https://github.com/sujayakar/rsdict

[2] https://github.com/sujayakar/arbolito

[3] https://github.com/jneem/teddy#teddy-1

[4] https://db.in.tum.de/~leis/papers/ART.pdf

Re: MIPS Becomes RISC-V

#57

Post by tyingq »

dralley wrote: post #53
MaxBarraclough wrote: post #36

Everyone's right to celebrate the success of RISC-V, but part of me thinks it's a shame that there's relatively little architectural diversity ( edit I should have said ISA diversity ) in modern CPUs. MIPS, Alpha, and Super-H, have all but faded away. Power/PowerPC is still out there somewhere though. Apparently they're still working on SPARC, too. [0] At least we'll always have the PS2. ...until the last one breaks,…

I'm curious if someone could explain the architectural differences between ppc64le and aarch64? I've always heard they are quite similar.

Since you mentioned ppc64le, there's also aarch64eb (arm64 in big endian mode). I saw that NetBSD supports it. It seems like support for other operating systems is limited mostly because of issues around booting...not the actual kernel or userland itself.

Re: MIPS Becomes RISC-V

#58

Post by bitwize »

st_goliath wrote: post #15

I just read the official statement[1] that's linked to in the article. Just so I get this straight: Wave Computing, the company that bought the remains of MIPS, is now (after bancruptcy) spinning it off as a separate company, that is going to work under the name MIPS, holds the rights to the MIPS architecture, but is doing RISC-V? [1] https://www.prnewswire.com/news-releases/wave-computing-and-...

Wave Computing is changing its name to MIPS, like how Tandy changed to RadioShack.

Re: MIPS Becomes RISC-V

#59

Post by Fordec »

MaxBarraclough wrote: post #36

Everyone's right to celebrate the success of RISC-V, but part of me thinks it's a shame that there's relatively little architectural diversity ( edit I should have said ISA diversity ) in modern CPUs. MIPS, Alpha, and Super-H, have all but faded away. Power/PowerPC is still out there somewhere though. Apparently they're still working on SPARC, too. [0] At least we'll always have the PS2. ...until the last one breaks,…

We need diversity for solving different problems, not for diversity sake.

What problem did MIPS solve in a unique way that others didn't? Because it wasn't desktop, mobile, embedded, graphics or AI.

Re: MIPS Becomes RISC-V

#60

Post by monocasa »

projektfu wrote: post #52
rst wrote: post #22

Earlier quoted context omitted.

Depends where you look. Hard to see IBM's z/Architecture dying out in that timeframe (the latest branding for S/360-derived mainframes), for example, and the embedded space is likely to remain an odd bestiary for quite some time.

Isn't z/Architecture just emulated on top of POWER? That's been my impression for a while.

They share RTL, but it's not just a POWER core with a z/Arch frontend.
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