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Apple’s A14 Packs 134M Transistors/mm²

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Re: Apple’s A14 Packs 134M Transistors/mm²

#171

Post by pas »

FPGAhacker wrote: post #126
ChuckMcM wrote: post #114

Earlier quoted context omitted.

This is where I believe the author goes astray: "Despite TSMC claiming a 1.8x shrink for N5, Apple only achieves a 1.49x shrink." TSMC does NOT say they have a 1.8x shrink for N5, they say for LOGIC you can get that, but for SRAM and Analog the results are 1.35x and 1.2x. Had they summed that together for a "typical SOC", which they also discuss (and one presumes that Apple makes typical SOCs) then the "theoretical"…

Wait, when node sizes where based off of a gate that meant logic gate? I always thought it was the transistor gate width.

https://spectrum.ieee.org/semiconductors/devices/a-better-wa...

https://www.youtube.com/watch?v=1kQUXpZpLXI (from 13:50, but the rest of the video is just amazing)

Re: Apple’s A14 Packs 134M Transistors/mm²

#172

Post by m3at »

ksec wrote: post #165
ChuckMcM wrote: post #57

I found this to be a pretty confusing article. I get that they are analyzing the new node, which is great, but the editorializing seems a bit premature to me. I also don't think the author understood the TMSC presentation. TMSC clearly said that is used a "model" of a typical SOC of 60% logic, 30% SRAM, and 10% analog. Then they said that for each category of thing, you could expect 1.8x, 1.35x, and 1.2x of shrink. I…

And the economic model now requires Leading Edge Fab to capture those value in a longer period of time. What used to be two years will be lengthen closer to three. >I'm curious how it compares when you look at 7nm introduction price per transistor vs todays price per transistor. And if you get the same ramp with the 5nm node what that would mean. First Gen N7 being ~10K+ per wafer while N5 being around ~13K with high…

The article quote ~17K for N5, do you have an other price reference or was it just a typo?

Re: Apple’s A14 Packs 134M Transistors/mm²

#173

Post by Hikikomori »

DiabloD3 wrote: post #120
ChuckMcM wrote: post #111

Earlier quoted context omitted.

I was referring to this: https://www.anandtech.com/show/15538/samsung-starts-mass-pro... Which has Samsung in production of their 7nm node this year as well.

Samsung's process seems to be consistently DOA.... by the time it is stabilized, its already behind everyone else. Consequently, almost all of Nvidia's current troubles stem from being unable to do all of their fabrication at TSMC, and the yields for Samsung 8nm being very poor. Nvidia recently canceled the 2x RAM variants of their 3070 and 3080 cards (and not because of insufficient GDDR6x, only the 3090 takes that)…

3080 also uses GDDR6x. The 3080/3090 shortage is because of GDDR6x availability from what I've been reading. We'll know when we see 3070 sales/deliveries.

Re: Apple’s A14 Packs 134M Transistors/mm²

#174

Post by Symmetry »

Tuna-Fish wrote: post #83
ineedasername wrote: post #22

What's the relative heat dissipation between logic & SRAM on a chip? The article talks about layering as a potential way forward for SRAM, but that would come with more complex TDP management, unless SRAM isn't burning watts at the same rate as the rest of the chip.

SRAM can potentially use very little power on modern processes, depending on how fast you want to be able to access it. If you are just making a relatively low-speed L3, getting rid of the heat produced in the SRAM itself will never be a problem. In general, the problem in SRAM layered on chip is considered to be that the stacked dies are a very good insulator, so the hot active die on the bottom will have heat dissi…

There's also smaller, but less efficient and slower 6 transistors cells versus larger but more efficient and faster 8 transistor cells to compare.

Re: Apple’s A14 Packs 134M Transistors/mm²

#175

Post by csharptwdec19 »

dodobirdlord wrote: post #129
phkahler wrote: post #92

Earlier quoted context omitted.

>> Second, companies exist for profit, and optimizing is not often the most profitable next step. That's true and reasonable. And after this 5nm node, TSMC has 3nm and IIRC 2nm. We are at the point where throwing more hardware at slow software is becoming a non solution. The good news is that in many cases there is a LOT of performance on the table on the software side.

The node size numbers have been made up for decades. Even if process shrinks bottom out two or three node shrinks from now there will still be improvements in process, materials, thermals, and packaging to allow things like greater z-axis stacking. And there's a ton of room for targeted improvement in things like vector instructions. That's not to say that there isn't an enormous amount of improvement available in so…

You don't even have to reach for SIMD to get better performance. Just stop letting crappy software get written.

I'm currently agonizing over an application that has an 80-120ms response time for 5 hops (including db writes). Yet I know many people who code in my language would find that number amazing for the work being done in those hops.

No SIMD. Nothing too crazy. Just well thought out processing flow and proper separation of the stupid.

Re: Apple’s A14 Packs 134M Transistors/mm²

#176

Post by jmnicolas »

Godel_unicode wrote: post #102
mucle6 wrote: post #78

Earlier quoted context omitted.

Buy an iPad pro because time and time again we have seen that optimizing is not a priority for the majority of business. I think the cynicism here is that if only these frontend developers would just learn to optimize we would all finally be better off. I think there are two factors that push against this though. First, if you learn to optimize then you can charge more for your labor, and you will likely get a job so…

Amazon and Google have published a truly tremendous amount of data about how fraction-of-a-second differences in loading time can have outsized impacts on bounce rate. It continues to be amazing to me that so many businesses just completely fail at understanding this basic truth. Speed is a competitive advantage. Doubly so when many of your competitors don't realize it.

And Amazon and Google are still slow ... Google maps is almost unusable on a slow dsl connection.

Re: Apple’s A14 Packs 134M Transistors/mm²

#177

Post by hinkley »

Dylan16807 wrote: post #146
hinkley wrote: post #63

Earlier quoted context omitted.

Video games used to call their pseudo-3d display 2.5D, or if they were feeling fancy, isomorphic. There is a little freedom in the Z axis, but not very much. But if speed of light matters to performance, then a chip design that increases the z axis decreases the euclidean distance between any two gates, which should (or at least could) matter to performance, right?

> But if speed of light matters to performance It barely matters. Gate delays and thermal limits outweigh distance by a huge factor. If you need to go further distances then you can wait one cycle and cover a relatively huge length.

> you can wait one cycle and cover a relatively huge length.

At the cost of increasing pipeline depth, right? We've been wrestling with that forever.

Re: Apple’s A14 Packs 134M Transistors/mm²

#178

Post by raydev »

hmottestad wrote: post #156
raydev wrote: post #138

Earlier quoted context omitted.

My 2013 high end 15" MBP gets pretty hot when I'm watching 1080p or higher videos. Chrome+YouTube is even worse, it even drops frames. Compiling Swift is even worse than that. I have a work-provided 16" MBP that does all these things effortlessly.

I don’t use Chrome much. Safari runs YouTube perfectly fine, even while running benchmarks for a dev project I work on at home.

Yeah, I understand Safari is easier on the CPU, unfortunately it doesn't allow for multiple profiles with separate histories/passwords. I also spend a bit of time on a Windows machine, and like having my history there too.

Re: Apple’s A14 Packs 134M Transistors/mm²

#179

Post by Dylan16807 »

hinkley wrote: post #177
Dylan16807 wrote: post #146

Earlier quoted context omitted.

> But if speed of light matters to performance It barely matters. Gate delays and thermal limits outweigh distance by a huge factor. If you need to go further distances then you can wait one cycle and cover a relatively huge length.

> you can wait one cycle and cover a relatively huge length. At the cost of increasing pipeline depth, right? We've been wrestling with that forever.

I would expect your pipeline steps to be far smaller than this scale.

We've been wrestling with the number of pipeline stages vs. the number of transistors in the critical path forever. Not so much physical distance.

Re: Apple’s A14 Packs 134M Transistors/mm²

#180

Post by hinkley »

eightysixfour wrote: post #71
hinkley wrote: post #64

Earlier quoted context omitted.

> you're still shoving 49% more transistors into the same overall amount of space What I fear is that we've hit the point where this is no longer a safe assumption. That we will be having people chase feature size numbers that don't actually result in a proportional increase in chip density. Transistors per square millimeter is closer to a measure we actually care about (speed of light and clock speed) instead of a b…

What from the article makes you think that's no longer a safe assumption? The 49% gain is exactly what happened going to 5nm. I don't think anyone actually cares about transistors/mm^2 at all, I think what we care about is perf or perf/watt for our specific workloads. I don't care if the chip is built with vacuum tubes if it is fast, efficient (per dollar and watt), and physically fits in the device I want it in.

First, because TSMC was aiming for 1.8x and Apple only saw 1.49, and I expect that not to improve going forward.

Second, one of us is reading that number wrong. They said 1.49x, not 49%.

In any other conversation, 2x is reducing feature size by 50%. 3x is 1/3 of the original, or reduced by 2/3. That means 1.8 is 45% smaller, and 1.49 is 32.9%.

Similarly, if you cut the pitch of a circuit in half you should see 4x as many transistors. If you could keep shrinking the space between transistors while shrinking the transistor, then going from "7" to "5" node should have been a 1.96x factor for areal density, not the 1.8x they claim, or the 1.49x Apple achieved.

I'm not saying they screwed up. As soon as nodes stopped measuring literal transistor size, it wouldn't take long for the names to be aspirational instead of descriptive. It's something they can name the project early on when the set of potential tech has been selected and some estimates have been made. For building a team it's fine. But I'm not on that team, I'm a customer (and current or former shareholder).

I think the consumer cares about the transistors per mm^2 (after the voltage and the instructions per second), not the node number. Especially when each foundry uses the same number to describe different densities. I shouldn't have to keep remembering that TSMC-7 = INTC-10. Numbers that are actual numbers, please.

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