161–170 of 183 posts
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It's not that hard: You just count the pins and divide by 3.
"As of 2019, the highest transistor count in any IC chip is Samsung's 1 TB eUFS (3D-stacked) V-NAND flash memory chip, with 2 trillion floating-gate MOSFETs (4 bits per transistor)." At 4 bits per transistor and 3 pins, how do you count the samsung bits? :)
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The problem is the assertion that "It's Apple's engineering and design". Engineering & design don't buy you the entire world's supply of the best in class fab capacity for some months: money does. It seems to me apple's marketing and product strategy has more to do with bringing in that money than actual engineering and design, contradicting the original assertion.
Apple wouldn't have shelled out the money to have first crack at 5nm if their design team couldn't commit to having a CPU design done in time. It's a huge R&D achievement to have such a complex design ready to go on a new node as the node launches. It speaks to extremely tight timelines and extremely close collaboration between TSMC and Apple.
Foundry sale price of $238/chip seems way too high. See e.g. https://www.cultofmac.com/658650/iphone-11-pro-max-productio... > Apple A13 processor that (is) supposedly is priced at $64.
Yeah, that $238/chip figure can't possibly be right. Apple's putting this chip in a $700 phone with at least a 50% margin. They're not blowing more than half the BoM on the SoC.
Is there a way to read the original report that this post was based upon?
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Samsung's process seems to be consistently DOA.... by the time it is stabilized, its already behind everyone else. Consequently, almost all of Nvidia's current troubles stem from being unable to do all of their fabrication at TSMC, and the yields for Samsung 8nm being very poor. Nvidia recently canceled the 2x RAM variants of their 3070 and 3080 cards (and not because of insufficient GDDR6x, only the 3090 takes that)…
Surely the ram variants use the same chips. Why cancel those because of yield? I wouldn't expect total demand to change by a significant amount...
I found this to be a pretty confusing article. I get that they are analyzing the new node, which is great, but the editorializing seems a bit premature to me. I also don't think the author understood the TMSC presentation. TMSC clearly said that is used a "model" of a typical SOC of 60% logic, 30% SRAM, and 10% analog. Then they said that for each category of thing, you could expect 1.8x, 1.35x, and 1.2x of shrink. I…
>I'm curious how it compares when you look at 7nm introduction price per transistor vs todays price per transistor. And if you get the same ramp with the 5nm node what that would mean.
First Gen N7 being ~10K+ per wafer while N5 being around ~13K with higher yield compare to N7 in the same stage. So N5 should still be cheaper.
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At the risk of sounding cheeky, Apple's engineering and design are the sole source of the money involved. Apple's involvement with TSMC also provides TSMC with an opportunity to learn from Apple. Nobody books an entire pure-play foundry without taking the time to figure out what they want to do with that manufacturing capacity in the first place.
Yeah, I'm tempted to say something like: it takes a while in your career before you figure out the enormous difference between companies who do engineering and design and companies who do design and engineering.
Isn't this mostly TSMC's achievement? Can't their other clients reach the same density?
Yes and no. TSMC's process node gives some hard upper limit to what can be built, but whether you can make your design that compact is an open question. One consideration is that while we think of each transistor as individual and isolated, in reality they are simply wells of n and p type silicon with some oxides and metal thrown in. Because of this we can get unwanted parasitic components and latches. A BJT transist…
https://en.wikipedia.org/wiki/Transistor_count
Has a big table listing a number of historical CPUs.
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Apple wouldn't have shelled out the money to have first crack at 5nm if their design team couldn't commit to having a CPU design done in time. It's a huge R&D achievement to have such a complex design ready to go on a new node as the node launches. It speaks to extremely tight timelines and extremely close collaboration between TSMC and Apple.
I'm not saying apple's engineering isn't good, just that it doesn't seem to be that exceptional. If the other companies couldn't have a design ready for 5nm then why would apple pay for the exclusivity rights?
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Are you the developer of iSH by any chance? If so, very cool project. Was it hard to get it published in the App Store?
I am a developer of iSH; tbodt did most of the interpreter work though. (Actually, he did most of the work on the app in general–there's a couple more of us who dabble in other parts of development, as well as support, marketing, compliance.) We're glad you like the project :) Getting iSH on the App Store did take some work on our side; we were in contact with Apple to get it approved and in compliance with the guide…