41–50 of 85 posts
How does it compare to the Arty A7 for $129?
Link to board: https://aliexpress.com/item/4000170042795.html
very impressive project, its a good time to get into fpga projects
It's much better than before, but it's still surprisingly difficult to buy a cheap (good) FPGA board. For example, the cheapest ECP5 on digikey (FPGA's go for a lot less than list if you're buying more than a few) is about $10 yet the cheapest proper development board is a lot more. The FPGA manufacturers like the margins, fine, but I'm surprised people who make boards like this one but for other things don't just ch…
Is there any published rationale for the RISC-V instruction encoding? A few months back I set out to write a software emulator of RISC-V for fun. I expected the instruction set encoding to lend itself well to a very simple implementation, eg. something you could decode in 5-10 lines of C plus some tables. But the instruction encoding is much more irregular than I expected: https://github.com/ucb-bar/riscv-sodor/blob/…
For example, the operands all stay in the same position, which prevents putting decode on the critical path before you can figure out which registers you need to read (which is doubly important for superscalar designs which need to compute the register dependence graph). Likewise, the sign-extend bit for immediates is always in the same place, providing relief for another potential critical path.
Is there any published rationale for the RISC-V instruction encoding? A few months back I set out to write a software emulator of RISC-V for fun. I expected the instruction set encoding to lend itself well to a very simple implementation, eg. something you could decode in 5-10 lines of C plus some tables. But the instruction encoding is much more irregular than I expected: https://github.com/ucb-bar/riscv-sodor/blob/…
Is there any published rationale for the RISC-V instruction encoding? A few months back I set out to write a software emulator of RISC-V for fun. I expected the instruction set encoding to lend itself well to a very simple implementation, eg. something you could decode in 5-10 lines of C plus some tables. But the instruction encoding is much more irregular than I expected: https://github.com/ucb-bar/riscv-sodor/blob/…
I'm not sure about publications that try to answer "why RISC-V?", but the specification often describes the rationales behind many of these kinds of decisions. The bit patterns are often designed to make it easier to write efficient hardware designs to implement them. For example, if an instruction encodes an "immediate" value, the most significant bit of the instruction will always hold that value's sign-extension b…
Earlier quoted context omitted.
Intel Stratix 10
Can you say more about why this one is the one? Is it better in quantitative ways or ease of use than competitors? Cheaper or more reliable? Etc
Earlier quoted context omitted.
We have open-source UEFI and openfirmware implementations already; is it really any more complicated then porting one and populating what I understand to be fairly standard interfaces for exposing device information to the operating system? Like... I'm sure it's not actually that easy, but what's the hard part once you've got working code execution from anyting resembling a normal compile chain?
I suspect GPU / display controller and associated licensing and patents are an even bigger obstacle.
Layman question: how many years before we get RISC-V desktops or Raspberry Pi like computers?
Desktops, perhaps never - 10 years? Alibaba seem to be funding some R&D in this direction, but I'm not too familiar (and I can't speak Chinese). It's certainly possible, but desktop processors aren't simple in any way. Regardless of absolute technical excellence, RISC-V only has to be better than ARM (in both specification and implementation, and cost, of course) which will be a moving target as RISC-V improves. Sing…
The HiFive Unleashed was released (and for sale) back in 2018. From memory, there was a limited run (priced at US$1k each), as it was targeted to specific types of developers looking to do further work improving the platform.
For example, Red Hat bought some and used them for improving the RISC-V support in Fedora. From memory, Richard Jones (@rwmj here on HN) was involved with it.
Layman question: how many years before we get RISC-V desktops or Raspberry Pi like computers?
Desktops, perhaps never - 10 years? Alibaba seem to be funding some R&D in this direction, but I'm not too familiar (and I can't speak Chinese). It's certainly possible, but desktop processors aren't simple in any way. Regardless of absolute technical excellence, RISC-V only has to be better than ARM (in both specification and implementation, and cost, of course) which will be a moving target as RISC-V improves. Sing…