41–50 of 113 posts
Earlier quoted context omitted.
Would you like to share how does one get into this line of work? I don't suppose there's an appropriate tutorial on egghead.io.
The standard path is more trodden than software development jobs -- ECE grad at a school with a good program.
One stark flailure of the Altera acquisition is there has been little by way of tool chain integration. This is a CPU with a bag on the side, and that bag needs people that write HDL and understand computer architecture to make good use of. It's not really a harsh critique, but a warning that the lower you go is an increasingly smaller number and expensive lot of folks. Intel's marketing arm can't distort that realit…
https://www.altera.com/products/design-software/embedded-sof...
One stark flailure of the Altera acquisition is there has been little by way of tool chain integration. This is a CPU with a bag on the side, and that bag needs people that write HDL and understand computer architecture to make good use of. It's not really a harsh critique, but a warning that the lower you go is an increasingly smaller number and expensive lot of folks. Intel's marketing arm can't distort that realit…
> that bag needs people that write HDL and understand computer architecture to make good use of Over time I suppose they could have some machine learning that automatically configures the FPGA based on which programs you are running and the types of computations they have historically used.
Nor do I think they will be invented soon. Machine learning is bad at doing discrete things, bad at things requiring zero mistakes, and bad at problems for which the answer can't be perfectly verified (due to needing to solve the halting problem).
Earlier quoted context omitted.
Learning an HDL isn't that hard. I was productive within a few weeks of starting to use VHDL. A former colleague is now an Altera/Intel FAE, I will ask how things are going the next time we meet up for a beer.
Writing HDL isn't hard but doing it right(much like with C) I would argue is the tricky part. The translation from Software -> Flip-Flops isn't nearly as natural and it's easy to try and apply SE techniques that while possible are totally unsuited for an FPGA.
If anyone is interested in using C# on a FPGA to learn take a look at https://hastlayer.com/project
Wow, someone managed to make something even worse than the "compile your C to an FPGA" tools you see occasionally. The model is just too different for these things to make sense 99% of the time. It's like trying to run general purpose code on a GPU, but even worse.
Typical programming languages run code one line at a time from the top to the bottom, occasionally calling functions or looping.
FPGA's instead have code which specifies a kind of circuit diagram of what is connected to what.
You can make something to translate one to the other, but by translating a programming language to a circuit diagram you usually end up bits of creating circuitry for each line of code, and then extra circuitry which makes each bit be activated in sequence.
That typically leaves 99.9% of the circuitry unused (deactivated) at any point in time. FPGA's don't have much space for circuitry, so by translating a program from C to an FPGA directly you'll usually end up with a huge design with a very low throughput, since the vast majority of the circuit is sitting idle most of the time.
Real FPGA designs will typically aim to use circuitry very sparingly, and keep as much of it in use as possible all the time to get maximal performance. Complex, sequential and non-performance critical tasks are typically not a good fit for an FPGA and are usually offloaded to a programmable processor instead.
One stark flailure of the Altera acquisition is there has been little by way of tool chain integration. This is a CPU with a bag on the side, and that bag needs people that write HDL and understand computer architecture to make good use of. It's not really a harsh critique, but a warning that the lower you go is an increasingly smaller number and expensive lot of folks. Intel's marketing arm can't distort that realit…
The FPGAs are programmable using OpenCL. That counts? https://www.altera.com/products/design-software/embedded-sof...
Earlier quoted context omitted.
> increasingly smaller number and expensive lot of folks. There is this sentiment on HN that people in EE/embedded space don't really get paid well (compared to the average Javascript-slinging frontend dev). Is this not true for HDL folks?
We get paid bank, there are very few of us, and the older you get and the more horror stories you've seen the more you're worth (unlike software). Gray in your beard is a feature, not a flaw. You're responsible for time critical and/or DSP things that are critical system architecture, and will never be outsourced (it's key IP, you'd be stupid to outsource that). Don't let anyone know, we have a good thing going on.
Earlier quoted context omitted.
Writing HDL isn't hard but doing it right(much like with C) I would argue is the tricky part. The translation from Software -> Flip-Flops isn't nearly as natural and it's easy to try and apply SE techniques that while possible are totally unsuited for an FPGA.
Witness the many systems that say they can translate something high level to HDL and how poorly they perform compared to an expert. It's so easy to produce logic that will run slowly or be glitchy, and most EE graduates have very limited exposure to designing logic.
It's a interesting space for sure and I'm definitely curious how these hybrid systems shake out.
One stark flailure of the Altera acquisition is there has been little by way of tool chain integration. This is a CPU with a bag on the side, and that bag needs people that write HDL and understand computer architecture to make good use of. It's not really a harsh critique, but a warning that the lower you go is an increasingly smaller number and expensive lot of folks. Intel's marketing arm can't distort that realit…
> that bag needs people that write HDL and understand computer architecture to make good use of Over time I suppose they could have some machine learning that automatically configures the FPGA based on which programs you are running and the types of computations they have historically used.