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Intel Shows Xeon Scalable Gold 6138P with Integrated FPGA, Shipping to Vendors

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Re: Intel Shows Xeon Scalable Gold 6138P with Integrated FPGA, Shipping to Vendors

#31

Post by Tade0 »

analognoise wrote: post #18
sannee wrote: post #5

Earlier quoted context omitted.

> increasingly smaller number and expensive lot of folks. There is this sentiment on HN that people in EE/embedded space don't really get paid well (compared to the average Javascript-slinging frontend dev). Is this not true for HDL folks?

We get paid bank, there are very few of us, and the older you get and the more horror stories you've seen the more you're worth (unlike software). Gray in your beard is a feature, not a flaw. You're responsible for time critical and/or DSP things that are critical system architecture, and will never be outsourced (it's key IP, you'd be stupid to outsource that). Don't let anyone know, we have a good thing going on.

Would you like to share how does one get into this line of work?

I don't suppose there's an appropriate tutorial on egghead.io.

Re: Intel Shows Xeon Scalable Gold 6138P with Integrated FPGA, Shipping to Vendors

#32

Post by ktta »

slrz wrote: post #15
ktta wrote: post #9

Earlier quoted context omitted.

I wouldn't be surprised if Intel came up with tools which help make use of the FPGA using higher languages like C. Xilinx is already pushing it's Vivado HLx which is pretty much that. I'm not aware of Altera's current offerings but they won't overlook this so easily.

> I wouldn't be surprised if Intel came up with tools which help make use of the FPGA using higher languages like C. These (almost by necessity) make you write code that doesn't look like any other C code. You can't just use some pre-existing C library and compile it to use FPGA resources. At that point, why not go a step further and just use a proper HDL?

Because although HDL doesn't look difficult syntax wise, it requires a very good understanding of logic gates. People need to pretty much take a course in digital design to be able to write something meaningful.

It took me a while to grok HDL and write working code (good, maintainable code aside) even though I took digital design courses.

Re: Intel Shows Xeon Scalable Gold 6138P with Integrated FPGA, Shipping to Vendors

#33

Post by monocasa »

jayonsoftware wrote: post #28

If anyone is interested in using C# on a FPGA to learn take a look at https://hastlayer.com/project

Wow, someone managed to make something even worse than the "compile your C to an FPGA" tools you see occasionally.

The model is just too different for these things to make sense 99% of the time. It's like trying to run general purpose code on a GPU, but even worse.

Re: Intel Shows Xeon Scalable Gold 6138P with Integrated FPGA, Shipping to Vendors

#34

Post by vvanders »

imbusy111 wrote: post #11
rjsw wrote: post #6

Earlier quoted context omitted.

Learning an HDL isn't that hard. I was productive within a few weeks of starting to use VHDL. A former colleague is now an Altera/Intel FAE, I will ask how things are going the next time we meet up for a beer.

How do you get into HDL and FPGAs? Seems like it will become a more and more important skill since all other avenues in performance improvement have come to a halt.

I like http://www.fpga4fun.com/ as a decent high level overview + a bunch of great tutorials.

Grab a Lattice CPLD/FPGA demo board($25-$50) and have at it!

Re: Intel Shows Xeon Scalable Gold 6138P with Integrated FPGA, Shipping to Vendors

#35

Post by __jal »

monocasa wrote: post #33
jayonsoftware wrote: post #28

If anyone is interested in using C# on a FPGA to learn take a look at https://hastlayer.com/project

Wow, someone managed to make something even worse than the "compile your C to an FPGA" tools you see occasionally. The model is just too different for these things to make sense 99% of the time. It's like trying to run general purpose code on a GPU, but even worse.

Why would anyone in their right mind try (or even want to try, except as a lark) this?

"...The input of Hastlayer can be a program written in dozens of programming languages (including several of the most popular ones as C#, C++, Python, PHP..."

Re: Intel Shows Xeon Scalable Gold 6138P with Integrated FPGA, Shipping to Vendors

#36

Post by aylons »

analognoise wrote: post #18
sannee wrote: post #5

Earlier quoted context omitted.

> increasingly smaller number and expensive lot of folks. There is this sentiment on HN that people in EE/embedded space don't really get paid well (compared to the average Javascript-slinging frontend dev). Is this not true for HDL folks?

We get paid bank, there are very few of us, and the older you get and the more horror stories you've seen the more you're worth (unlike software). Gray in your beard is a feature, not a flaw. You're responsible for time critical and/or DSP things that are critical system architecture, and will never be outsourced (it's key IP, you'd be stupid to outsource that). Don't let anyone know, we have a good thing going on.

Hey, thank you for that. I really needed this motivation at this point in my life as an EE (RF, RTL and PCB level).

Re: Intel Shows Xeon Scalable Gold 6138P with Integrated FPGA, Shipping to Vendors

#37

Post by rjsw »

aseipp wrote: post #24
rjsw wrote: post #6

Earlier quoted context omitted.

Learning an HDL isn't that hard. I was productive within a few weeks of starting to use VHDL. A former colleague is now an Altera/Intel FAE, I will ask how things are going the next time we meet up for a beer.

Learning an HDL isn't that hard. But it's a very small part of the overall flow for real development, and arguably it's one of the easier parts anyway... That's sort of the "problem", more or less. Even very well-oiled products like the Amazon F1 and Intel's new acceleration cards are pretty non-trivial to use unless you're an experienced engineer, and they clearly spent a lot of time polishing off the roughest edges…

I have an ARM+FPGA system (Xilinx Zynq), I don't use the supplied BSP either.

Re: Intel Shows Xeon Scalable Gold 6138P with Integrated FPGA, Shipping to Vendors

#38

Post by kev009 »

sannee wrote: post #5
kev009 wrote: post #4

One stark flailure of the Altera acquisition is there has been little by way of tool chain integration. This is a CPU with a bag on the side, and that bag needs people that write HDL and understand computer architecture to make good use of. It's not really a harsh critique, but a warning that the lower you go is an increasingly smaller number and expensive lot of folks. Intel's marketing arm can't distort that realit…

> increasingly smaller number and expensive lot of folks. There is this sentiment on HN that people in EE/embedded space don't really get paid well (compared to the average Javascript-slinging frontend dev). Is this not true for HDL folks?

I work on operating systems, which is similarly niche (but probably overall easier to learn and low risk vs fabbing ASICs) an it is very bi-modal. Sr. circuit designers can write their ticket, but you have a lot of warm bodies surrounding them at large companies.

Re: Intel Shows Xeon Scalable Gold 6138P with Integrated FPGA, Shipping to Vendors

#39

Post by kev009 »

Tade0 wrote: post #31
analognoise wrote: post #18

Earlier quoted context omitted.

We get paid bank, there are very few of us, and the older you get and the more horror stories you've seen the more you're worth (unlike software). Gray in your beard is a feature, not a flaw. You're responsible for time critical and/or DSP things that are critical system architecture, and will never be outsourced (it's key IP, you'd be stupid to outsource that). Don't let anyone know, we have a good thing going on.

Would you like to share how does one get into this line of work? I don't suppose there's an appropriate tutorial on egghead.io.

The standard path is more trodden than software development jobs -- ECE grad at a school with a good program.

Re: Intel Shows Xeon Scalable Gold 6138P with Integrated FPGA, Shipping to Vendors

#40

Post by bonestamp2 »

kev009 wrote: post #4

One stark flailure of the Altera acquisition is there has been little by way of tool chain integration. This is a CPU with a bag on the side, and that bag needs people that write HDL and understand computer architecture to make good use of. It's not really a harsh critique, but a warning that the lower you go is an increasingly smaller number and expensive lot of folks. Intel's marketing arm can't distort that realit…

> that bag needs people that write HDL and understand computer architecture to make good use of

Over time I suppose they could have some machine learning that automatically configures the FPGA based on which programs you are running and the types of computations they have historically used.

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