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Intel Shows 2.5D FPGA at ISSCC

eetimes.com

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Re: Intel Shows 2.5D FPGA at ISSCC

#31

Post by ploek »

guitarbill wrote: post #29
watersb wrote: post #24

Earlier quoted context omitted.

I am re-building my ZFS array with consumer parts. GIGABYTE GA-X150M-PRO ECC Kingston 16GB ECC DIMM KVR21E15D8/16 Pentium G4600 CPU Toys arrive in a couple of days. Total outlay was $220. When I first built my storage box, in 2009, the AMD CPUs all supported ECC DRAM, but I could not find a motherboard-chipset-BIOS setup that would actually implement it.

I think that's why so many people go with the older HP microservers. Super cheap, nice form factor, just add ECC RAM and HDDs.

Yes! I'm dreading the day when my N36L dies. So far I've only had to replace the PSU fan. And it's weird that no other manufacturer has anything like it. Compact case, not too noisy, houses 4 disks, runs FreeNAS.

Re: Intel Shows 2.5D FPGA at ISSCC

#32

Post by rwg »

guitarbill wrote: post #29
watersb wrote: post #24

Earlier quoted context omitted.

I am re-building my ZFS array with consumer parts. GIGABYTE GA-X150M-PRO ECC Kingston 16GB ECC DIMM KVR21E15D8/16 Pentium G4600 CPU Toys arrive in a couple of days. Total outlay was $220. When I first built my storage box, in 2009, the AMD CPUs all supported ECC DRAM, but I could not find a motherboard-chipset-BIOS setup that would actually implement it.

I think that's why so many people go with the older HP microservers. Super cheap, nice form factor, just add ECC RAM and HDDs.

I have an HP MicroServer N40L that I bought several years ago, and it's almost a doorstop now. Its CPU (dual-core 1.5 GHz AMD Turion II Neo) is slow and doesn't support AES-NI. It maxes out at 8 GB of RAM (16 GB of RAM if the stars align and it likes the RAM you bought). It has one GigE port, and SATA ports are limited to 3 Gbps (SATA II). Expansion is limited to an eSATA port, USB 2.0 ports, a low-profile PCIe 2.0 x1 slot, and a low-profile PCIe 2.0 x16 slot.

It's okay as a NAS that mostly sits idle and occasionally serves up unencrypted data at GigE speeds or less. For more demanding tasks, it's woefully underpowered.

Re: Intel Shows 2.5D FPGA at ISSCC

#34

Post by vorticalbox »

anonova wrote: post #9
qeternity wrote: post #5

AMD really needs to start competing on price. Match Intel and Nvidia performance, at 75% TCO.

Given early benchmarks are showing that the Ryzen 7 1700X ($390) is performing similarly to the Intel Core i7-6900K ($1050), they definitely are going in that direction. http://hothardware.com/news/amds-ryzen-7-1700x-delivers-i7-6...

If that's true they are vastly under cutting the market and I do see these cheap prices staying for the next gen.

I could be AMD trying to steal market share.

Re: Intel Shows 2.5D FPGA at ISSCC

#35

Post by m_mueller »

m_mueller wrote: post #20
jcoffland wrote: post #14

Earlier quoted context omitted.

It's actually quite difficult to use AVX512 and have it pay off significantly unless you design something to specifically take advantage of it.

Exactly. IMO doing GPGPU is actually easier than porting code to use vectorisation, since GPU cores are quite a bit more capable (allow branching/context switches, just with a performance penalty) than the CPUs vector units (vector code AFAIK completely breaks if you try to do an early return on one unit). I'm waiting for the day when the CPU designers learn from GPU and just give us full OpenMP kernel support, such…

> just give us full OpenMP kernel support, such that you can use both multicore and vectorization by just scattering the OpenMP

oops. s/OpenMP/OpenCL

Re: Intel Shows 2.5D FPGA at ISSCC

#36

Post by tyfon »

peatmoss wrote: post #10
qeternity wrote: post #5

AMD really needs to start competing on price. Match Intel and Nvidia performance, at 75% TCO.

I think they could carve out a niche by being the chip maker that produces a trustworthy computing environment that supports blob-free computing without the equivalent of Intel Management Engine. That plus your point about TCO could be a nice way of competing with Intel.

AMD has their own thing called TrustZone[1].

If you read past the marketing speak it is made to allow software to run without the user being able to poke at it. I assume this is for DRM, but who knows what is running there.

[1] https://www.amd.com/en-us/innovations/software-technologies/...

Re: Intel Shows 2.5D FPGA at ISSCC

#37

Post by gcp »

m_mueller wrote: post #20
jcoffland wrote: post #14

Earlier quoted context omitted.

It's actually quite difficult to use AVX512 and have it pay off significantly unless you design something to specifically take advantage of it.

Exactly. IMO doing GPGPU is actually easier than porting code to use vectorisation, since GPU cores are quite a bit more capable (allow branching/context switches, just with a performance penalty) than the CPUs vector units (vector code AFAIK completely breaks if you try to do an early return on one unit). I'm waiting for the day when the CPU designers learn from GPU and just give us full OpenMP kernel support, such…

Note that AVX512 actually addresses many of the issues that made SIMT code so inefficient on CPUs. It's not just widening the vectors, but also adding predication/masking etc.

I do fully agree that SIMT is a much easier programming model than SIMD.

Re: Intel Shows 2.5D FPGA at ISSCC

#38

Post by gcp »

pshposh wrote: post #22
webaholic wrote: post #15

reddit has some benchmarks (rumored): http://i.imgur.com/9bXzF5B.png https://videocardz.com/65913/how-fast-is-ryzen

Why do both of these feature only the physics benchmark? The second link illustrates that Intel still wins in single core performance.

I don't think there's any question that Intel will win in single-thread performance. AMD has never stated the opposite. They will, though, manage to deliver much more cores despite only being a tiny bit behind in single-core, which is a very big difference from e.g. Bulldozer.

Re: Intel Shows 2.5D FPGA at ISSCC

#39

Post by coldtea »

mrb wrote: post #3

I should have linked to the second page: http://www.eetimes.com/document.asp?doc_id=1331317&page_numb... Relevant quote: "AMD said its upcoming Zen x86 core fits into a 10 percent smaller die area than Intel’s currently shipping second-generation 14nm processor. Analysts and even Intel engineers in the session said the Zen core is clearly competitive though many confidential variables will determine whether the die a…

>AMD said its upcoming Zen x86 core fits into a 10 percent smaller die area than Intel’s currently shipping second-generation 14nm processor.

Sounds totally irrelevant.

Re: Intel Shows 2.5D FPGA at ISSCC

#40

Post by vosper »

coldtea wrote: post #39
mrb wrote: post #3

I should have linked to the second page: http://www.eetimes.com/document.asp?doc_id=1331317&page_numb... Relevant quote: "AMD said its upcoming Zen x86 core fits into a 10 percent smaller die area than Intel’s currently shipping second-generation 14nm processor. Analysts and even Intel engineers in the session said the Zen core is clearly competitive though many confidential variables will determine whether the die a…

> AMD said its upcoming Zen x86 core fits into a 10 percent smaller die area than Intel’s currently shipping second-generation 14nm processor. Sounds totally irrelevant.

Maybe the implication is that a 10% smaller die means fewer transistors per chip, and therefore lower failure rate per chip, meaning that they get more working chips out of each wafer or something? And maybe that makes them less expensive, so that they could undercut Intel?
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