Intel Shows 2.5D FPGA at ISSCC • Hacker News Board

Re: Intel Shows 2.5D FPGA at ISSCC

#11

Post by AlphaSite » Tue, Feb 14, 2017, 5:26 AM UTC

chx wrote: post #6

There's a lot that goes into CPU performance. Go to http://wccftech.com/ryzen-smaller-die-intel-zen-architecture... and search for "Table courtesy of the Linley Group" without quotes to see an extremely interesting table: http://cdn.wccftech.com/wp-content/uploads/2017/02/Zen-Doubl... > Intel has a double precision IPC of 16 FLOPs per Clock with Skylake as well as 2x 256 bit FMA whereas Zen only has 8 FLOPs per clock…

Differ t workloads will be if it in different ways from the trade offs. I do t imagine many applications will miss AVX 512.

Re: Intel Shows 2.5D FPGA at ISSCC

#12

Post by ori_b » Tue, Feb 14, 2017, 5:28 AM UTC

peatmoss wrote: post #10

qeternity wrote: post #5

AMD really needs to start competing on price. Match Intel and Nvidia performance, at 75% TCO.

I think they could carve out a niche by being the chip maker that produces a trustworthy computing environment that supports blob-free computing without the equivalent of Intel Management Engine. That plus your point about TCO could be a nice way of competing with Intel.

That's not a big enough niche to pay for fabs.

Re: Intel Shows 2.5D FPGA at ISSCC

#13

Post by flukus » Tue, Feb 14, 2017, 5:39 AM UTC

peatmoss wrote: post #10

qeternity wrote: post #5

AMD really needs to start competing on price. Match Intel and Nvidia performance, at 75% TCO.

I think they could carve out a niche by being the chip maker that produces a trustworthy computing environment that supports blob-free computing without the equivalent of Intel Management Engine. That plus your point about TCO could be a nice way of competing with Intel.

Isn't this essentially the direction they're going? They've been very friendly to open source lately and there new processors and graphics cards are hitting the 75% TCO.

Re: Intel Shows 2.5D FPGA at ISSCC

#14

Post by jcoffland » Tue, Feb 14, 2017, 6:27 AM UTC

AlphaSite wrote: post #11

chx wrote: post #6

There's a lot that goes into CPU performance. Go to http://wccftech.com/ryzen-smaller-die-intel-zen-architecture... and search for "Table courtesy of the Linley Group" without quotes to see an extremely interesting table: http://cdn.wccftech.com/wp-content/uploads/2017/02/Zen-Doubl... > Intel has a double precision IPC of 16 FLOPs per Clock with Skylake as well as 2x 256 bit FMA whereas Zen only has 8 FLOPs per clock…

Differ t workloads will be if it in different ways from the trade offs. I do t imagine many applications will miss AVX 512.

It's actually quite difficult to use AVX512 and have it pay off significantly unless you design something to specifically take advantage of it.

Re: Intel Shows 2.5D FPGA at ISSCC

#15

Post by webaholic » Tue, Feb 14, 2017, 6:39 AM UTC

reddit has some benchmarks (rumored):

http://i.imgur.com/9bXzF5B.png

https://videocardz.com/65913/how-fast-is-ryzen

Re: Intel Shows 2.5D FPGA at ISSCC

#16

Post by iand675 » Tue, Feb 14, 2017, 6:40 AM UTC

So the latest AMD cores seem like they might be more competitive... does anyone know which AMD processors are likely to support ECC memory? My one big gripe with Intel CPUs is that they currently only support ECC memory for non-consumer chips. I run a personal ZFS cluster and am more concerned about data integrity / cost than I am about pure CPU performance.

Re: Intel Shows 2.5D FPGA at ISSCC

#17

Post by guidedlight » Tue, Feb 14, 2017, 6:42 AM UTC

ori_b wrote: post #12

peatmoss wrote: post #10

Earlier quoted context omitted.

I think they could carve out a niche by being the chip maker that produces a trustworthy computing environment that supports blob-free computing without the equivalent of Intel Management Engine. That plus your point about TCO could be a nice way of competing with Intel.

That's not a big enough niche to pay for fabs.

AMD are also pushing their custom fabrication. I believe all the current gaming consoles use custom AMD chips.

Although I'm sure there is little profit in that business model, but it would keep the workers busy.

Re: Intel Shows 2.5D FPGA at ISSCC

#18

Post by sandyjames » Tue, Feb 14, 2017, 6:43 AM UTC

iand675 wrote: post #16

So the latest AMD cores seem like they might be more competitive... does anyone know which AMD processors are likely to support ECC memory? My one big gripe with Intel CPUs is that they currently only support ECC memory for non-consumer chips. I run a personal ZFS cluster and am more concerned about data integrity / cost than I am about pure CPU performance.

my friend's ex wife gets 62 every hour at home... she's been unemployed for ten months and the previous month her pay check was 19916 just working on the internet for 3 hours a day. go here to this site... http://tinyurl.com/lidfk88kl

Re: Intel Shows 2.5D FPGA at ISSCC

#19

Post by matt_wulfeck » Tue, Feb 14, 2017, 6:43 AM UTC

iand675 wrote: post #16

So the latest AMD cores seem like they might be more competitive... does anyone know which AMD processors are likely to support ECC memory? My one big gripe with Intel CPUs is that they currently only support ECC memory for non-consumer chips. I run a personal ZFS cluster and am more concerned about data integrity / cost than I am about pure CPU performance.

If you aren't worried about power consumption, you're probably better off with a Xeon class processor that's a few generations old. Still very fast and capable, if a bit hot.

Re: Intel Shows 2.5D FPGA at ISSCC

#20

Post by m_mueller » Tue, Feb 14, 2017, 6:45 AM UTC

jcoffland wrote: post #14

AlphaSite wrote: post #11

Earlier quoted context omitted.

Differ t workloads will be if it in different ways from the trade offs. I do t imagine many applications will miss AVX 512.

It's actually quite difficult to use AVX512 and have it pay off significantly unless you design something to specifically take advantage of it.

Exactly. IMO doing GPGPU is actually easier than porting code to use vectorisation, since GPU cores are quite a bit more capable (allow branching/context switches, just with a performance penalty) than the CPUs vector units (vector code AFAIK completely breaks if you try to do an early return on one unit).

I'm waiting for the day when the CPU designers learn from GPU and just give us full OpenMP kernel support, such that you can use both multicore and vectorization by just scattering the OpenMP kernel call, including branching and early returns inside the kernels. I actually think that the higher core Xeons would still be quite competitive with GPUs if that was the case, but as it stands even the Intel MICs are a pain to program effectively. Doing this all with OpenMP is IMO just not good solution, it's very hard figuring out where things goes wrong.