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AMD announces the Spartan UltraScale+ FPGA family

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Re: AMD announces the Spartan UltraScale+ FPGA family

#81

Post by nsteel »

Aromasin wrote: post #73
nsteel wrote: post #38

Earlier quoted context omitted.

> they're in every 5G base station Just a tiny nitpick to your great answer but Nokia's 5G base station stuff (Reefshark) is built around ASICs. I would expect others do the same. There's some reasoning at https://www.electronicdesign.com/technologies/embedded/artic... https://www.nokia.com/about-us/news/releases/2020/06/15/noki...

The ReefShark ASIC sits alongside an FPGA which acts akin to an IPU. I know only because I played my own small part in the design. It was originally meant to be entirely FPGA-based, but they got hit with some severe supply constraints by Intel and Xilinx, which is why cost keeps getting discussed. Prices have dropped back down to stable numbers again since mid-last year, but at the time ASICs ended up being more affo…

We (outside Wireless) heard the Intel silicon didn't perform/yield and the original designs became infeasible, prompting a sudden mad scramble. I didn't realise it was originally planned to be FPGA-based. Interesting, thanks.

Very glad to hear things have improved.

Re: AMD announces the Spartan UltraScale+ FPGA family

#82

Post by kjs3 »

MegaDeKay wrote: post #61

It would be incredible if AMD made some open source moves with their FPGAs as they did with their GPUs. That would allow open source tools like Yosys and nextptr to work with them easily vs. the painstaking reverse engineering efforts this now requires. Xilinx Vivado is a massive beast of a thing. https://github.com/YosysHQ

I think the issue is there are different market drivers at play. GPUs are more 'visible' than FPGAs to consumers; there's probably a couple of orders of magnitude more people pushing for open source/hackable drivers for GPUs than FPGAs (at least today). So AMD doesn't feel the pressure in the FPGA market, and it's 'easier' to maintain the status quo. I suspect we'll have to wait for a use case where somewhere near as many average users are actually thinking about their FPGA vendor as they do about their GPU vendor before things will change. Maybe an AI/ML application?

Re: AMD announces the Spartan UltraScale+ FPGA family

#83

Post by [deleted] »

willis936 wrote: post #34
dfox wrote: post #32

Earlier quoted context omitted.

You mean something like this: https://www.amd.com/en/products/system-on-modules/kria.html Spartan is the glue-logic family for applications that either do not require any kind of CPU core at all or where some simple soft-core (MicorBlaze, x51, hand crafted state machine...) suffices.

Yes I do mean the Kria line, but one for this new Spartan Ultrascale+. I already buy packaged versions of $30 FPGAs because it alleviates most of the integration effort.

[deleted]

Re: AMD announces the Spartan UltraScale+ FPGA family

#85

Post by duskwuff »

stephen_g wrote: post #19
shrubble wrote: post #3

Earlier quoted context omitted.

MiSTer is about 110K , this can go up to 218K. Probably this new FPGA is something like BGA package, since it has over 500 I/O pins. Also not available this year: "AMD Spartan UltraScale+ samples and evaluation kits are expected to be available for sampling and evaluation in the first half of 2025."

This isn't "a" new FPGA, there'll be like 50+ (or even hundreds of) SKUs, many will be various BGA/chip scale packages (with different numbers of pins available) but not necessarily all of them. The Spartan line, being the lowest level of Xilinx's FPGAs, have traditionally had a few versions in TQFP packages. I wouldn't be incredibly surprised if they did with this new version (although it's probably less and less li…

There weren't any TQFP packages in 7-series either, and I don't expect that to change for US+. Even Spartan-6 only had that package for their smallest parts (XC6SLX4/LX9).

Re: AMD announces the Spartan UltraScale+ FPGA family

#86

Post by Aromasin »

anonymousDan wrote: post #28

Shame it is only PCI-e Gen 4.

You don't seem to get PCIe Gen 5 outside of the top-end devices it seems. Agilex 7 has it on the Intel side with the R-Tile devices (including a hard CXL IP too which is lovely), but their recently announced Agilex 5 (the UltraScale+ competitor) only host PCIe 4.0 x8. I guess it takes up too much in terms of resources to double the throughput on a low-power device.

Re: AMD announces the Spartan UltraScale+ FPGA family

#87

Post by vrinsd »

This "announcement" is basically a no-op. It's very likely not a new device but taking something like an Artix and just re-branding it and then limiting access to device features via software(Vivado). The same was done for 'Spartan-7' -- it was NOT a new device, just an existing design where they removed the SERDES block.

What made Spartan-6 unique was in addition to having transcievers was the hardened DDR memory controller.

If you read this announcement, DDR support is done via 'soft' memory controller, which chews up a lot of resources and makes meeting timing frustrating, forcing use of Xilinx's MIG IP.

Re: AMD announces the Spartan UltraScale+ FPGA family

#88

Post by willis936 »

blihp wrote: post #80
willis936 wrote: post #78

Earlier quoted context omitted.

Do companies really gamble on their supply chain that hard?

They don't have a choice. FPGA's aren't like vanilla logic chips: they are highly proprietary both in terms of their specific hardware functionality as well as software tool chains and you can't second source them. Some of the larger customers are using them for government contracts (think military and space applications) where they are signing up products they are contractually on the hook for from years to decades.

Yes I know. So any product being developed today or in the next year would be done on a well established option that will be produced for many more years. It still isn't clear to me why such a long runway on the announcement does for anyone. It shouldn't be changing anyone's plans.

Re: AMD announces the Spartan UltraScale+ FPGA family

#89

Post by jeff-davis »

bayindirh wrote: post #27
dailykoder wrote: post #9

Earlier quoted context omitted.

They enable a lot of crazy defence products. A well known german product for example is the Iris-T from Diehl Defence. Highly accurate and exceptional engineering. But I guess FPGAs are in most defence products nowadays. I think the biggest reason is that you can build/verify your own hardware without having to go through the expensive ASIC manufacturing Edit: I just realized that these are some literal killer apps.…

> But I guess FPGAs are in most defence products nowadays. Yes. > I think the biggest reason is that you can build/verify your own hardware without having to go through the expensive ASIC manufacturing. Plus, you don't give out your secrets to fabs, too. Design, verify, launch, discard, without the need for signing an NDA.

"Plus, you don't give out your secrets to fabs, too."

That's a perfect answer to my question, thank you.

Also many other great answers in this thread, but I don't have much to add.

Re: AMD announces the Spartan UltraScale+ FPGA family

#90

Post by blharr »

DrStartup wrote: post #53
jeff-davis wrote: post #6

What are some killer apps for FPGAs? What major products do they enable?

I think we’re going to see a greatly increased use of FPGAs in AI applications. They can be very good at matrix multiplication. Think about an AI layer that tunes the FPGA based on incoming model requirements? Need an LPU like groq? Done. I would bet Apple Silicon gets some sort of FPGA in the neural engine.

But ASICs perform way faster and more efficiently. I doubt even the gain that you would get from "retuning" the FPGA would not increase enough compared to the benefit from a general purpose processor, GPU, or an ASIC
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