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TSMC 2nm Process Disclosure – How Does It Measure Up?

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Re: TSMC 2nm Process Disclosure – How Does It Measure Up?

#51
post #2

So, Intel has its better "18A" process and we have no idea when they will start production at scale and where? Weird.

The first Intel product on 18A is the "Panther Lake" CPU for laptops.

According to what Intel claims, it will be launched in H2 2025, i.e. with commercial availability either in October or in December, depending on how quickly Intel will succeed to improve the yields of the 18A process.

Re: TSMC 2nm Process Disclosure – How Does It Measure Up?

#52

Earlier quoted context omitted.

If that were totally true you would expect to see more or less uniform ratios of HP/HD cells mixes across different product types, but that's very much not the case. Dennard scaling may be dying but it's not dead yet. You can still sacrifice efficiency to gain performance. It's not zero sum.

What product types do you have in mind exactly? Even big server chips now use a huge fraction of their area for power-sipping "efficiency core" designs that wouldn't be out of place in a mobile chip. Power is king.

Those efficiency cores would put a full core from just a few years ago to shame, and data center chips have always contained a majority niche focused on throughput and perf/watt over latency. That's nearly always been focused on somewhere closer to the 45° part of the scurve than more on the top.

Re: TSMC 2nm Process Disclosure – How Does It Measure Up?

#53

Earlier quoted context omitted.

14nm or so is kind of a sweet spot for general purpose chip design right now, because later nodes turn out to have higher overall per-transistor cost despite the improvement in density and area. Of course this may well change over time as even finer production nodes get developed and the existing nodes then move closer to the trailing edge.

The article linked in another comment pointed out that cost per transistor keeps falling, and it's just the fast increasing fixed costs that make it seem otherwise. https://semianalysis.com/2022/07/24/the-dark-side-of-the-sem...

Right, but the "fast increasing fixed costs" are what really matters usually. It's not just perception.

Re: TSMC 2nm Process Disclosure – How Does It Measure Up?

#54
Does anyone know why Nvidia chose to re-use the 4N process for their Blackwell series? From everything I've read, 3N is mature and is already in full production, yet Nvidia chose to just reuse 4N. It seems very much unlike Nvidia to leave performance on the table.

Re: TSMC 2nm Process Disclosure – How Does It Measure Up?

#55

Does anyone know why Nvidia chose to re-use the 4N process for their Blackwell series? From everything I've read, 3N is mature and is already in full production, yet Nvidia chose to just reuse 4N. It seems very much unlike Nvidia to leave performance on the table.

My guess is it's related to yield and/or large die sizes making them more susceptible to defects. I expect architectural changes in the Blackwell series matter more than performance improvements from process node.

Re: TSMC 2nm Process Disclosure – How Does It Measure Up?

#56
post #49
post #32

Earlier quoted context omitted.

What do you tbink is holding RiscV core design back? Is it the IP situation?

The RISC-V core designs that have emerged so far don't have nearly the amount of silicon dedicated to optimizing IPC as one sees in ARM, x86 and others: predictors, sophisticated caches, complex instruction dispatch, deep pipelines, etc. That stuff isn't provided with the RISC-V core designs you get for free or license at low cost, because it's fabulously expensive to develop, tied to the ISA and core designs for whi…

Only reasons it wouldn't all boil down to, `it wouldn't matter`. E.G. If something else that does have it gets released to free as in beer levels why bother?

Unless modern civilization ends or an easier alternative is released eventually anything Open Source will get good enough.

Re: TSMC 2nm Process Disclosure – How Does It Measure Up?

#57

Does anyone know why Nvidia chose to re-use the 4N process for their Blackwell series? From everything I've read, 3N is mature and is already in full production, yet Nvidia chose to just reuse 4N. It seems very much unlike Nvidia to leave performance on the table.

The answer is probably profit margin. It's also not unusual at all for Nvidia to leave performance on the table in terms of production nodes. I mean just look at the RTX 3000 series which was made with Samsung 8LPH, categorized as a "10nm node". Even at the time, for a late 2020 launch, TSMC already had several generations which were better, in both the "7nm" an "5nm" categories.

Re: TSMC 2nm Process Disclosure – How Does It Measure Up?

#58
post #10

Super interesting. Now what we really need is for Raspberry Pi to make a 2nm version so that the power usage becomes more acceptable for Wildlife and biodiversity use cases. Please, please Raspberry Pi, also make a 2nm version Actually, I think it's broadcom I need to ask that from isn't it ? (Although then I think it would almost become a Jetson) Please please NVidia make a 1nm Jetson, the planet needs you to.

The node is not nearly as relevant as the design of the SoC to optimize for low power, and the large amount of supporting software work to actually make it real. Phone SoCs are generally optimized for this, but the lifetime of a part in the market is too short for something like the raspberry pi.

Re: TSMC 2nm Process Disclosure – How Does It Measure Up?

#59

Does anyone know why Nvidia chose to re-use the 4N process for their Blackwell series? From everything I've read, 3N is mature and is already in full production, yet Nvidia chose to just reuse 4N. It seems very much unlike Nvidia to leave performance on the table.

N3 is mature and is already in full production for small Mobile SoC only.

The Blackwell goes up to ~750mm2 it is a completely different beast. And Nvidia is already having trouble trying to fill up their Blackwell on a higher capacity, relatively mature N4 Node. Imagine doing it on an expensive N3, and then charge $4999 only to get outrage as rip off on HN and reddit.

Generally speaking the larger die size, high performance chip tends to be a node behind simply because all the leading edge node and tools aren't even designed for them but are specifically aiming at Mobile SoC. Then you add in cost issue and yield.

Re: TSMC 2nm Process Disclosure – How Does It Measure Up?

#60
post #32

Earlier quoted context omitted.

Riscv doesn't need smaller nm. It just needs someone to actually design and release a good core design. 14nm (or 4 or anything in between) is perfectly suffient to make a Riscv chip 10x faster than any Riscv that currently exist.

What do you tbink is holding RiscV core design back? Is it the IP situation?

One of the things that could really help here is to create a license along the lines of "GPL for hardware" and then for a company like Google or Meta to release a design under it. The design wouldn't even have to be state of the art; something with performance equivalent to a ten year old x64 design would be valuable enough that people would use it for things if it was free.

But the larger value is that then people could use it as a starting point for modifications, which would in turn have to be released under the same license. Soon you have a diverse set of designs to choose from and we can start getting open hardware into common use because using any of those designs would be a cost savings over buying or designing something equivalent, but because the license requires an open design the user can then create custom firmware etc. and we might finally start to do something about the IoT security nightmare.

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