TSMC 2nm Process Disclosure – How Does It Measure Up?
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Re: TSMC 2nm Process Disclosure – How Does It Measure Up?
#2Weird.
Re: TSMC 2nm Process Disclosure – How Does It Measure Up?
#3So, Intel has its better "18A" process and we have no idea when they will start production at scale and where? Weird.
> In terms of the overreaching Power, Performance, and Area (PPA), the paper states that the process delivers a 30% power improvement or 15% performance gain and >1.15x density versus the previous 3nm node.
Since I know the nm numbers are meaningless anymore, it’s kind of an insult to the math of 3 to 2 to call these sorts of minor improvements that.
Re: TSMC 2nm Process Disclosure – How Does It Measure Up?
#4So, Intel has its better "18A" process and we have no idea when they will start production at scale and where? Weird.
The whole thing is incredibly frustrating to read because no one is providing any sort of data or graphs that are beyond something you would see in a commercial. > In terms of the overreaching Power, Performance, and Area (PPA), the paper states that the process delivers a 30% power improvement or 15% performance gain and >1.15x density versus the previous 3nm node. Since I know the nm numbers are meaningless anymore…
https://semiwiki.com/wp-content/uploads/2025/02/Figure-1.jpg>
You see, the bars go up and to the right as indicated by the arrow. The thing at the top right, which is under discussion, is more than fifteen times better than the thing on the bottom left.
This is a huge achievement.
Re: TSMC 2nm Process Disclosure – How Does It Measure Up?
#5Earlier quoted context omitted.
The whole thing is incredibly frustrating to read because no one is providing any sort of data or graphs that are beyond something you would see in a commercial. > In terms of the overreaching Power, Performance, and Area (PPA), the paper states that the process delivers a 30% power improvement or 15% performance gain and >1.15x density versus the previous 3nm node. Since I know the nm numbers are meaningless anymore…
I think that this graph sums it up pretty precisely: https://semiwiki.com/wp-content/uploads/2025/02/Figure-1.jpg > You see, the bars go up and to the right as indicated by the arrow. The thing at the top right, which is under discussion, is more than fifteen times better than the thing on the bottom left. This is a huge achievement.
> We took the graph image, pulled it into Excel and created an Excel graph overlaying it with the 28nm bar normalized to 1 and then entering values for the other bars until they matched the graph. If we then build a set of bars starting at 28nm = 1 scaled up based on the TSMC announced node to node power improvements we get a total improvement of less than 9x. Nodes from N28 to N10 match well but from N7 on the bars on the graph show more improvement per node than TSMC has announced. Just the N3 to N2 bars on the graph show a 55% improvements versus the announced 30% improvement.
> …
> It isn’t clear what may be driving this difference, but it is a big disconnect. This may be why the graph was removed from the final paper.
Re: TSMC 2nm Process Disclosure – How Does It Measure Up?
#6So, Intel has its better "18A" process and we have no idea when they will start production at scale and where? Weird.
Intel says that 18A will be a thing around mid of 2025, so 4-6 months from now, I think.
Then it will upgrade to HVM between Q3 and Q1 iirc
Re: TSMC 2nm Process Disclosure – How Does It Measure Up?
#7Re: TSMC 2nm Process Disclosure – How Does It Measure Up?
#8Re: TSMC 2nm Process Disclosure – How Does It Measure Up?
#9Re: TSMC 2nm Process Disclosure – How Does It Measure Up?
#10Please, please Raspberry Pi, also make a 2nm version
Actually, I think it's broadcom I need to ask that from isn't it ?
(Although then I think it would almost become a Jetson)
Please please NVidia make a 1nm Jetson, the planet needs you to.