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TSMC 2nm Process Disclosure – How Does It Measure Up?

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Re: TSMC 2nm Process Disclosure – How Does It Measure Up?

#31

Post by wuschel »

zozbot234 wrote: post #26
adgjlsfhk1 wrote: post #22

Earlier quoted context omitted.

Riscv doesn't need smaller nm. It just needs someone to actually design and release a good core design. 14nm (or 4 or anything in between) is perfectly suffient to make a Riscv chip 10x faster than any Riscv that currently exist.

14nm or so is kind of a sweet spot for general purpose chip design right now, because later nodes turn out to have higher overall per-transistor cost despite the improvement in density and area. Of course this may well change over time as even finer production nodes get developed and the existing nodes then move closer to the trailing edge.

Interesting! Could you perhaps point me towards the source where I could read up on the state of the art of chip manufacturing and the implications coming from the respective manufacture processes?

Re: TSMC 2nm Process Disclosure – How Does It Measure Up?

#32

Post by wuschel »

adgjlsfhk1 wrote: post #22
ramshanker wrote: post #15

How much would the Non-Recurrent Cost associated with designing a RISC-V CPU using this 2nm? EDA Tools, Photo-Masks, One Time Chip Design Engineer Cost, Simulation/Virtual Verification and so on. I mean every thing till tape-out.

Riscv doesn't need smaller nm. It just needs someone to actually design and release a good core design. 14nm (or 4 or anything in between) is perfectly suffient to make a Riscv chip 10x faster than any Riscv that currently exist.

What do you tbink is holding RiscV core design back? Is it the IP situation?

Re: TSMC 2nm Process Disclosure – How Does It Measure Up?

#33

Post by zozbot234 »

wuschel wrote: post #31
zozbot234 wrote: post #26

Earlier quoted context omitted.

14nm or so is kind of a sweet spot for general purpose chip design right now, because later nodes turn out to have higher overall per-transistor cost despite the improvement in density and area. Of course this may well change over time as even finer production nodes get developed and the existing nodes then move closer to the trailing edge.

Interesting! Could you perhaps point me towards the source where I could read up on the state of the art of chip manufacturing and the implications coming from the respective manufacture processes?

Isn't that what sites like the OP are for?

Re: TSMC 2nm Process Disclosure – How Does It Measure Up?

#34

Post by thunderbird120 »

zozbot234 wrote: post #20
thunderbird120 wrote: post #18

Earlier quoted context omitted.

>Intel on 18A is literally TSMC's 3nm process + backside power delivery, which means more power efficiency, performance also less heat. That's a pretty serious abuse of the word "literally" given that they have nothing in common except vague density figures which don't mean that much at this point. Here's a line literally from the article >Based on this analysis it is our belief that Intel 18A has the highest perform…

The death of Dennard scaling means that power efficiency is king, because a more power efficient chip is also a chip that can keep more of its area powered up over time for any given amount of cooling - which is ultimately what matters for performance. This effect becomes even more relevant as node sizes decrease and density increases.

If it were that simple fabs wouldn't offer a standard cell libraries in both high performance and high density varieties. TSMC continues to provide both for their 2nm process. A tradeoff between power efficiency and raw performance continues to exist.

Re: TSMC 2nm Process Disclosure – How Does It Measure Up?

#35

Post by [deleted] »

monocasa wrote: post #24
selectodude wrote: post #19

Earlier quoted context omitted.

3nm was over a half billion. So if costs are going up at the same rate, over a billion dollars. https://semianalysis.com/2022/07/24/the-dark-side-of-the-sem...

That article refers to those charts by McKinsey as "incorrect" and instead gives a figure of $50M-$75M for 3nm.

[deleted]

Re: TSMC 2nm Process Disclosure – How Does It Measure Up?

#36

Post by zozbot234 »

thunderbird120 wrote: post #34
zozbot234 wrote: post #20

Earlier quoted context omitted.

The death of Dennard scaling means that power efficiency is king, because a more power efficient chip is also a chip that can keep more of its area powered up over time for any given amount of cooling - which is ultimately what matters for performance. This effect becomes even more relevant as node sizes decrease and density increases.

If it were that simple fabs wouldn't offer a standard cell libraries in both high performance and high density varieties. TSMC continues to provide both for their 2nm process. A tradeoff between power efficiency and raw performance continues to exist.

A standard cell can be a critical performance bottleneck as part of a chip, so it makes sense to offer "high performance" cell designs that can help unblock these where appropriate. But chip cooling operates on the chip as a whole, and there you gain nothing by picking a "higher raw performance" design.

Re: TSMC 2nm Process Disclosure – How Does It Measure Up?

#37

Post by hcfman »

magicalhippo wrote: post #13
hcfman wrote: post #10

Super interesting. Now what we really need is for Raspberry Pi to make a 2nm version so that the power usage becomes more acceptable for Wildlife and biodiversity use cases. Please, please Raspberry Pi, also make a 2nm version Actually, I think it's broadcom I need to ask that from isn't it ? (Although then I think it would almost become a Jetson) Please please NVidia make a 1nm Jetson, the planet needs you to.

The current Pi 5 is on a 16nm node[1], down from 28nm for the Pi 4. So, far off needing a bleeding edge node[2] to see further improvements. [1]: https://chipwise.tech/our-portfolio/raspberry-pi-5/ [2]: https://www.tsmc.com/english/dedicatedFoundry/technology/log...

The Pi is great! Just saying, running a Pi with an object detector on batteries draws around 9W. That's big batteries and solar or wildlife use cases. But think how cool it would be if it could run on 2W.

Having said that. The Jetson runs at around 7W doing that and a lot faster inference. Just a lot more expense. Likely the Jetson will eventually be something like 2nm. So maybe we see around 4W at that time running an object detector. And of course the Jetson has the memory and processor together on it's modules so everything can benefit. Just dropping the power on the Pi for the processor leaves that out.

But thanks for the links

Re: TSMC 2nm Process Disclosure – How Does It Measure Up?

#38

Post by thunderbird120 »

zozbot234 wrote: post #36
thunderbird120 wrote: post #34

Earlier quoted context omitted.

If it were that simple fabs wouldn't offer a standard cell libraries in both high performance and high density varieties. TSMC continues to provide both for their 2nm process. A tradeoff between power efficiency and raw performance continues to exist.

A standard cell can be a critical performance bottleneck as part of a chip, so it makes sense to offer "high performance" cell designs that can help unblock these where appropriate. But chip cooling operates on the chip as a whole, and there you gain nothing by picking a "higher raw performance" design.

If that were totally true you would expect to see more or less uniform ratios of HP/HD cells mixes across different product types, but that's very much not the case. Dennard scaling may be dying but it's not dead yet. You can still sacrifice efficiency to gain performance. It's not zero sum.

Re: TSMC 2nm Process Disclosure – How Does It Measure Up?

#39

Post by zozbot234 »

thunderbird120 wrote: post #38
zozbot234 wrote: post #36

Earlier quoted context omitted.

A standard cell can be a critical performance bottleneck as part of a chip, so it makes sense to offer "high performance" cell designs that can help unblock these where appropriate. But chip cooling operates on the chip as a whole, and there you gain nothing by picking a "higher raw performance" design.

If that were totally true you would expect to see more or less uniform ratios of HP/HD cells mixes across different product types, but that's very much not the case. Dennard scaling may be dying but it's not dead yet. You can still sacrifice efficiency to gain performance. It's not zero sum.

What product types do you have in mind exactly? Even big server chips now use a huge fraction of their area for power-sipping "efficiency core" designs that wouldn't be out of place in a mobile chip. Power is king.

Re: TSMC 2nm Process Disclosure – How Does It Measure Up?

#40

Post by wongarsu »

m00dy wrote: post #7

for those who are in the industry, it's just a marketing term.

A marketing term that will have to change. For the last couple decades every new, denser process generation just took the previous number and divided it by sqrt(2). That doesn't really work beyond 2nm.

Intel invented a new number they can count down. Do we already know what naming scheme TSMC will adopt for the next generations?

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